Achieving Uniform Device Performance by Using Advanced Process Control and SuperScan™

As CMOS technologies advance beyond the 45nm feature size, device architectures and semiconductor manufacturing processes are becoming more complex. Process variations from multiple process modules lead to disparities in device performance. Several key processes such as gate patterning are typically under advanced process control (A PC). However, a critical challenge for APC is the embedded SiGe (eSiGe) selective epitaxial process (used for PFET stress-engineering), which may have across-wafer radial variation that significantly impact PFET overlap capacitance (C-ov) and threshold voltage (V-tsat). As a counter-measure to address this issue in a 45nm SOI CMOS platform for advanced logic products, the SuperScan (TM) option was employed for the PFET extension implant using a Varian VIISta (TM) high-current single-wafer implanter. The Super Scan technology implants wafers with tailored implant dose maps, to correct for non-implant-related across-wafer process non-uniformities. The Super Scan technique resulted in significant reduction of across-wafer variation in PFET C-ov and V-tsat, without degradation in I-on/I-off. A major achievement was the reduction in variation of CMOS ring oscillator static leakage vs. frequency, along with the elimination of high-leakage outliers, both of which improved product targeting with respect to speed grades.