Recently, a 22nm fully depleted gate-first SOI technology (FDSOI) has shown significant promise as a low-cost alternative to FinFETs with devices that are tunable between low-leakage and high-performance regimes. [1] The 22nm FDSOI PFET utilizes a SiGe channel with epitaxial grown raised source/drain (RSD) to define the junction profile, strain the channel, and facilitate contact formation. The pRSD epitaxial growth is typically a two-layer process with a main layer of SiGe:B followed by a capping layer of Si. Because the RSD epitaxy grows along the spacer dielectric, it results in a parasitic capacitance to the Gate electrode which then contributes to the total MOSFET capacitance and degrades AC device performance. Since the thickness of the main layer as well as the cap layer has a strong influence on this parasitic capacitance (Cgd), the RSD thickness should, in theory, be kept as low as possible. This is necessary to achieve the maximum AC and RF device performance. However, decreasing the RSD thickness below a certain level has the undesirable effect of DC performance drop. Therefore, another approach is needed to decrease Cgd further without degrading the drive current. In this paper we present one of the strongest methods to increase FDSOI technology AC/RF device performance, namely faceted raised source/drain epitaxial growth. Faceted pRSD epitaxy effectively decouples the RSD height and Cgd, lowering the parasitic capacitance not by reduced total RSD height, but rather by eliminating the shared wall between the Gate and the RSD. This simple approach has two desirable outcomes: 1) low Cgd & AC performance gain, and 2) low electrical variability via suppressing the influence of RSD height variation. The primary electrical response from faceted pRSD is the lowering of Cgd up to 25% at matched DC performance at zero gate bias; and this resulted in approximately 5% ring oscillator performance and ca. 20GHz RF p-Ft improvement. Other advantages of faceted pRSD are the selectivity in epitaxial growth and electrical variability. As mentioned previously, in a typical FDX device, RSD height needs to be controlled very tightly to achieve low device variability in DC transistor parameters (Ieff, Vtsat, Ioff) and Cgd. With faceted pRSD, however, this “shared wall” between Gate and RSD is liminated. We observed that the Cgd did not respond over a range of +/- 13% in main layer thickness, which led to a tight distribution of transistor parameters. Put another way, with faceted RSD, the primary need of a tight control over the pRSD thickness is eliminated. References [1] R. Carter and et al., "22nm FDSOI technology for emerging mobile, Internet-of-Things, and RF applications," in IEDM16, San Fransisco, 2016.

We report an experimental pFET with 420GHz fT, which to the best of our knowledge is the highest value reported for a silicon pFET. The transconductance is 1800uS/um. The technology is fully depleted silicon on insulator (FDSOI) with the pFET channel formed by SiGe condensation. This outstanding performance is achieved by a combination of layout and process optimization which minimizes capacitance and maximizes compressive strain on the channel. The technology features a high-k metal gate and short gate length (20nm drawn) in addition to the SiGe channel for high mobility.

As CMOS technologies advance beyond the 45nm feature size, device architectures and semiconductor manufacturing processes are becoming more complex. Process variations from multiple process modules lead to disparities in device performance. Several key processes such as gate patterning are typically under advanced process control (A PC). However, a critical challenge for APC is the embedded SiGe (eSiGe) selective epitaxial process (used for PFET stress-engineering), which may have across-wafer radial variation that significantly impact PFET overlap capacitance (C-ov) and threshold voltage (V-tsat). As a counter-measure to address this issue in a 45nm SOI CMOS platform for advanced logic products, the SuperScan (TM) option was employed for the PFET extension implant using a Varian VIISta (TM) high-current single-wafer implanter. The Super Scan technology implants wafers with tailored implant dose maps, to correct for non-implant-related across-wafer process non-uniformities. The Super Scan technique resulted in significant reduction of across-wafer variation in PFET C-ov and V-tsat, without degradation in I-on/I-off. A major achievement was the reduction in variation of CMOS ring oscillator static leakage vs. frequency, along with the elimination of high-leakage outliers, both of which improved product targeting with respect to speed grades.

This article shows the importance of source/drain extension dopant species on the performance of embedded silicon-germanium strained silicon on insulator p-metal oxide semiconductor field effect transistor (MOSFET) devices, in which the activation was done using only high temperature ultrafast annealing technologies. BF2 and boron were investigated as source/drain extension dopant species. In contrast to unstrained silicon p-MOSFETs, boron source/drain extension implantations enhance device performance significantly compared to devices with BF2 source/drain extension implantations. Measurements show a 30% mobility enhancement and lower external resistance for the devices with boron source/drain extension implantations. The reason for this lies in the amorphization nature of BF2 implantations. Remaining defects after implant annealing affect the stress transfer from the embedded silicon-germanium and the overall hole mobility which leads to the observed performance degradation. Furthermore, TCAD simulations reveal that the mobility degradation with BF2 source/drain extension implantations is equivalent to almost 36% strain relaxation of the embedded silicon-germanium.

Asymmetric halo and extension implantations are examined by simulation for their usability in 45 and 32 nm technology high performance silicon on insulator metal oxide semiconductor field effect transistors (SOI-MOSFETs). Tilted halo and extension implantations from the source side show higher saturation currents and lower drain overlap and junction capacitances, which improve the intrinsic MOSFET power delay product. Furthermore the asymmetric doping profile leads to an inverter chain speed benefit. The stronger short channel effect, present in these devices, can be reduced by a low dose drain side halo implantation simultaneously maintaining a transistor performance improvement from asymmetric doping. This optimized transistor design is successfully transferred from the 45 into the 32 nm technology.

We present an overview of partially-depleted silicon-on-insulator (PD-SOI) CMOS transistor technologies for high-performance microprocessors. To achieve a "high performance per watt" figure of merit, transistor technology elements like PD-SOI, strained Si, aggressive junction scaling, and asymmetric devices need hand-in-hand development with multiple-core and power-efficient designs. These techniques have been developed, applied, and optimized for 45nm SOI volume manufacturing at GLOBALFOUNDRIES in Dresden. To enable further transistor scaling to 32nm design rules, high-K metal-gate (HKMG) technology is key. Gate-first and replacement-gate HKMG integration as well as future strained Si technologies like strained silicon directly bonded on SOI and embedded Si:C are discussed.

We have extensively studied the impact of advanced annealing schemes for highperformance SOI logic technologies. Starting with the 130 nm technology node, we introduced spike rapid thermal annealing (sRTA). Continuous temperature reduction combined with implant scaling helped to improve transistor performance and short channel behavior. During the development of the 90 nm technology we evaluated flash lamp and laser annealing (FLA). These techniques became an essential part of the 65 nm node. At this node we also faced major challenges in terms of compatibility with new materials like SiGe as well as the need for reduction of process parameter fluctuations. Scaling will be continued with the 45 nm technology node towards a truly diffusionless process.

We present here the substitutional carbon dependence of ClusterCarbon implant energy and dose, and anneal parameters such as solid phase epitaxial regrowth (SPER) temperature and various high temperature millisecond flash anneal conditions. With a multiple implant sequence of carbon implants one can obtain a fairly uniform carbon profile and we show that it provides better carbon substitution [C](sub) when compared to a single implant. It is been established that optimizing the percentage Of [C](sub) requires an SPER anneal temperature <850 degrees C followed by a millisecond anneal. We show that carbon substitution increases with SPER temperature up to 800 degrees C and decreases beyond this temperature supporting the fact that carbon has a significant probability of being excited out of its substitutional site beyond 850 degrees C. We report here that SPER anneal with an additional millisecond flash anneal that provides highest carbon substitution, [C](subs) > 2%. For a given millisecond anneal and for implants with various energies and doses we show that the percentages Of [C](sub) increases linearly with the fraction of carbon dopants within the amorphous layer. (C) 2008 Elsevier B.V. All rights reserved.

As device geometries scale, the formation of the SDE becomes increasingly difficult and increasingly important. For advanced technologies, new methods such as ultra-low-energy boron implantation and millisecond annealing (flash or laser) are necessary to achieve the required junction characteristics. In addition, these Processes must be compatible: with the remainder of the process flow, which might include advanced dielectrics, stress technologies, SOI, etc. The emergence of ClusterBoron as a high productivity alternative for the low energy implant creates interest in device performance possible in a realistic process flow.This paper will present an evaluation of the use of ClusterBoron for the PMOS SIDE in an advanced 65nm logic process which includes laser annealing, e-SiGe stress layers and SOL The conventional process uses a BF2 SDE process. Complete device characteristics will be shown. comparing the ClusterBoron SIDE to the conventional BF2. It will be shown that the ClusterBoron process achieves better boron activation, leading to enhanced transistor drive current. It will also be shown that the ClusterBoron is compatible with the SiGe stress layers and SOI structure. In summary, ClusterBoron presents an attractive alternative to the conventional BF2 process for advanced PMOS SDE.