An Optimized Fast Stair-case Set Pulse with Variable Width for Phase Change Random Access Memory

Phase change random access memory tend to provide the write speed close to that of DRAM to expand applications in stand-alone and embedded filed. The period of set operation is the key parameter to determine the write speed. In this paper, a method for optimizing each step width of a stair-case pulse is proposed. The width of each step can be adjusted according to the cell percentage for set current acquired from the lowest resistance point in the Resistance-Current curve. This method can solve the heating inconsistency problem of set operation and is beneficial to speed and set resistance distribution. The experiment results are gathered across a 16 Kb blocks of a 4 Mb PCRAM chip with 40 nm CMOS process. The resulting optimized stair-case set pulse speed is less than 100 ns. (C) 2020 The Electrochemical Society ("ECS"). Published on behalf of ECS by IOP Publishing Limited.