Abstract In this work, we report a structurally optimized design of 7-nm InGaAs-SOI complementary FinFET, and demonstrate thermal reliability of InGaAs-based logic device and circuit-level behavior over a wide temperature range of ˜200 to ˜700 K. The proposed 7-nm InGaAs–SOI FinFET with optimized fin architecture achieves Vth values of 0.50 and 0.60 V for the n-type and p-type FinFETs, respectively, with an exceptional ON/OFF current ratio of 6.21×1010, subthreshold swing (SS) of 67.44 mV/dec, and drain-induced barrier lowering (DIBL) of 59.20 mV/V. It is observed that the InGaAs–SOI FinFET device exhibits strong self-heating characteristics and superior short-channel immunity at elevated operating temperatures compared to conventional Si CMOS FinFETs and wide-bandgap technologies such as SiC. Furthermore, to mitigate the inherent imbalance at the circuit level, an asymmetric complementary inverter is designed using a 4:1 pMOS-to-nMOS Fin ratio to offset the electron–hole mobility disparity. The optimized binary inverter sustains reliable switching operation and exhibits improved voltage gain with maintaining positive noise margins up to 700 K at a low supply voltage of 1.5 V. These findings highlight the promise of InGaAs-SOI CMOS FinFETs for high-speed logic applications operating in elevated-temperature environments, such as defense and space systems.
Abstract Electrochemical mechanical polishing (ECMP) is a promising technique for achieving efficient and low-damage planarization of 4H-SiC. However, the difficulty in balancing electrochemical oxidation and mechanical removal during ECMP limits both processing efficiency and surface quality. In this study, the anodic oxidation behavior of 4H-SiC in NaCl solution under different voltages was investigated through electrochemical experiments. Equivalent circuit modeling and fitting analysis clarified the evolution of oxide-layer growth, passivation, and breakdown. Based on these findings, a periodic stepwise voltage strategy was proposed for rough and fine polishing to dynamically regulate the balance between electrochemical oxidation and mechanical removal. Mechanistically, the oxide layer was mechanically removed by CeO2 abrasives, while periodic voltage switching suppressed excessive oxidation and repeated local oxide-layer breakdown. The process achieved material removal rate (MRR) of 1.497 μm h-1 and 0.751 μm h-1 during rough and fine polishing, respectively, and reduced the surface roughness (Ra) from 5.531 nm to 0.587 nm within 1 h. This work provides a strategy for coordinating electrochemical oxidation and mechanical removal in 4H-SiC ECMP.
This study presents a comprehensive numerical optimization of single and tandem photovoltaic cells utilizing novel Cu 3 InSnS 5 colloidal quantum dots (CQDs) as absorbers. These quaternary CQDs have emerged as a compelling class of low-dimensional materials due to their tunable optoelectronic properties and compliance with the Restriction of Hazardous Substances (RoHS) directive. A multi-scale simulation framework is employed, combining the envelope function approximation to predict size-dependent quantum confinement effects, Rigorous Coupled-Wave Analysis (RCWA) for optical modeling, and the Solar Cell Capacitance Simulator (SCAPS-1D) for device-level electrical optimization. By systematically tuning the CQD radius, buffer layer, and absorber thickness, the optimized single-junction cell achieves a power conversion efficiency of 11.53% under standard AM1.5G illumination, significantly surpassing the current experimental benchmark of <0.1%. Furthermore, a tandem architecture is designed to minimize thermalization losses, yielding an impressive efficiency of 31.97% under AM1.5G. Under indoor LED illumination (1250 lx), the single and tandem cells attain efficiencies of 12.13% and 22.21%, respectively. These findings underscore the immense potential of Cu 3 InSnS 5 CQDs for dual indoor/outdoor energy harvesting, particularly for powering low-light Internet of Things (IoT) devices.
We evaluated the detailed behavior of defects generated during plasma etching and subsequential low temperature annealing by using low-temperature photoluminescence (PL) spectroscopy. As a result, W-line originating from tri-interstitial Si and X-line originating from quad-interstitial Si were observed, regardless of annealing. Furthermore, multiple point measurements taken at 30 μm intervals that interstitial Si is generated during the etching process and additionally diffuses approximately 120 μm from the trench processing region into the unprocessed region. The diffusion distance of interstitial Si was unchanged before and after annealing at 300 and 400 °C, suggesting diffusion was complete by the etching process. Moreover, during the 400 °C annealing, clustering of interstitial Si was promoted. Furthermore, it was confirmed that the formation of carbon and oxygen-related defects is caused by the increase in interstitial silicon from the trench region, and that these defects diffuse over equivalent distances. This indicates that interstitial Si is strongly correlated with the generation and diffusion of associated compound defects. Based on these results, this study demonstrated the diffusion of point defects beyond the plasma-etched region, which has not been addressed in previous studies, and clarified the formation and diffusion behavior of defects during the low-temperature annealing process.
The performance assessment and radiation response of dual-spacer FinFET and NCFinFET technology at the device and circuit levels are presented in this work. At the device level, NCFinFET architectures have a larger I on / I off ratio and a lower subthreshold swing than traditional FinFETs due to internal voltage amplification caused by the negative capacitance layer. The NCFinFET with a Si 3 N 4 + HfO 2 gate stack performs better among the evaluated architectures. Single Event Transient simulations are used to analyze NCFinFET-based logic gates, including an inverter, NAND, NOR, AND, OR, and buffer, under radiation exposure. Heavy ions are injected into sensitive nodes to assess charge collection and transient behavior over a wide range of Linear Energy Transfer values. The results show that the logic gates operate accurately and reliably, while NCFinFET logic gates exhibit lower charge collection than conventional FinFET gates, indicating improved radiation hardness. The buffer and NOR gates have faster recovery times and higher robustness. Circuit-level metrics, such as propagation delay, power consumption, and noise margin, are also evaluated. Overall, the proposed dual-spacer NCFinFET architecture improves both electrical performance and radiation resilience, making it a promising candidate for high-performance, low-power, and radiation-hardened digital applications.
Wet etching of delafossite CuGaO 2 and CuCrO 2 thin films was investigated for the first time. CuGaO 2 films were exposed to concentrated HCl, nitric acid, and aluminum etchant at varying temperatures, with etch rates dependent on temperature. Concentrated HCl produced the highest etch rates. CuCrO 2 films were etched using an HCl–HNO 3 mixture at 40 °C–60 °C and chromium-based etchants at dilutions of 1:5 to 1:10. The fastest etching was observed in the 1:5 dilution, and slower rates were achieved through higher dilutions or lower temperatures. Optical microscopy confirmed well-defined patterns, achieving feature sizes as small as 19 μm. Preliminary Arrhenius analysis indicated thermally activated etching behavior, highlighting the strong influence of etchant chemistry on the etching mechanism.
In this work, a novel stoichiometry engineering approach using multi-step anodic oxidation (ANO) is proposed to fabricate a high-performance charge-trapping memory (CTM) device on an n-type 4H-SiC substrate. By precisely modulating the anodization process at room temperature, a functional gate stack comprising a sub-stoichiometric AlO x charge trapping layer and a fully oxidized Al 2 O 3 blocking layer was successfully formed. Material characterizations, including transmission electron microscopy (TEM) and energy dispersive X-ray spectroscopy (EDX), confirmed the distinct oxygen-deficient nature of the trap-rich AlO x layer and the stoichiometric perfection of the Al 2 O 3 barrier. Electrically, the fabricated Al / Al 2 O 3 / AlO x / SiO 2 /4 H - SiC device exhibits a massive clockwise capacitance-voltage (C-V) hysteresis and an exceptionally low gate leakage current (below 10 −10 A), verifying the efficacy of both the engineered defect states and the blocking mechanism. A significant normalized capacitance window ( Δ C ′ ) of 3.30 was achieved and stably maintained over 100 continuous program and erase cycles. The effective charge density stored in the device is around Δ N eff = 2.48 × 10 12 cm −2 . The underlying charge trapping and de-trapping mechanisms are comprehensively elucidated using energy band models. This study demonstrates a highly promising, cost-effective, and ALD-free method for integrating reliable non-volatile memory on SiC platforms.
The characteristics of β -Ga 2 O 3 /Al 2 O 3 /Pt capacitors fabricated via the dummy-SiO 2 ( d-SiO 2 ) process at 800 °C under O 2 (D-O 2 ), N 2 (D-N 2 ), and 3% H 2 (D-H 2 ) atmospheres were investigated. The surface of Ga 2 O 3 after the d-SiO 2 process was as smooth as that after the sulfuric acid-hydrogen peroxide mixture treatment (Control). The flatband voltage ( V fb ) hysteresis decreased as follows: Control (0.76 V) > D-H 2 (0.56 V) > D-N 2 (0.43 V) > D-O 2 (0.37 V). The interface state density of the D-O 2 capacitor was significantly reduced to 6 × 10 11 cm −2 eV −1 at −0.4 eV from conduction band. The V fb shift caused by the electron traps according to the near-interface trap model under positive bias stress substantially improved for the capacitors fabricated by the d-SiO 2 process. The poor characteristics of the Control capacitor are due to the presence of the unstable layer on the Ga 2 O 3 surface. The improved electrical characteristic of the d-SiO 2 capacitors is due to the modified Ga 2 O 3 surface, which eliminated the unstable Ga 2 O 3 layer. This is the result of hydrogen contained within the dummy SiO 2 layer supporting the removal of Ga 2 O 3 . The difference in the decomposition reaction of Ga 2 O 3 due to the atmosphere gas of the d-SiO 2 process leads to differences in electrical properties.
Transistor Technology plays a crucial role in human life. The aim is to increase the number of applications and increase speed in a single Integrated Circuit (IC) of Transistor Technology. This paper reviews the conventional transistor devices (Planar MOSFET, MESFET, DGMOSFET, DGMOSFET with Dual Material, and DGMOSFET with High-k Materials), modern transistor devices (FinFET and SOI FinFET), and advanced transistor devices (GAAFET (Gate All Around Nanosheet FET, Gate All around Nanowire FET and Tree FET). Different aspects, such as Drain Induced Barrier Leakage (DIBL), Leakage Current, Short Channel Effects (SCE), and Subthreshold Swing (SS), influence the performance of FETs. A comparison study shows that the Nanosheet Field Effect Transistor (NSFET) is the best transistor device in the semiconductor industry due to its low power performance, and also provides low parasitic capacitance, low temperature sensitivity, better electrostatic control, higher switching capacity, and good considerable scaling. The review also explores the development of next-generation transistor architectures such as Forksheet FETs, Complementary FETs, Vertical Transport FETs, Quantum Dot Transistors, Single-Electron Transistors, and Qubit Devices, which are among the most promising candidates under active research and are being considered as potential replacements for nanosheet FETs.
Novel ternary nanocomposite films composed of polyvinyl chloride (PVC) integrated with nano Mn 0.95 Mg 0.05 WO 4 and polyaniline (PANI) at diverse concentrations (0–4 wt%) were successfully produced using co-precipitation and solution casting procedures. The combined incorporation of semiconducting tungstate and conductive polymer into the PVC matrix produces significant improvements in optical and dielectric properties. X-ray diffraction (XRD) examination verifies the successful integration of crystalline Mn 0.95 Mg 0.05 WO 4 fillers into the amorphous PVC matrix. The nanocomposites demonstrate adjustable optical characteristics, with direct band gaps consistently decreased from 5.07 eV (PVC) to 3.07 eV, alongside notable increases in refractive index and extinction coefficient. Photoluminescence investigations reveal excitation-dependent emission tunability spanning blue-violet to orange-white spectral areas, with Commission Internationale de l’Éclairage (CIE) coordinates validating the tunable color output. Dielectric studies indicate that the ternary system containing 3 wt% PANI attains peak performance, demonstrating significantly improved dielectric constant and AC conductivity alongside diminished dielectric loss. Electric modulus analysis verifies non-Debye relaxation phenomena regulated by hopping conduction pathways. The significant enhancement in nonlinear optical properties further emphasizes the promise of these nanocomposites. The aggregated findings indicate that PVC/Mn 0.95 Mg 0.05 WO 4 /PANI ternary nanocomposites are potential multifunctional materials for flexible energy storage devices, adjustable optical filters, UV-blocking coatings, and photonic applications.
The use of transparent, and lead-free shielding materials is very important for safety in nuclear and medical environments. The present glasses offer excellent transparency and formability, optimizing their structural stability and photon attenuation properties. The introduction of BaO/ZnO into borate glasses increases the density ( ρ ) from 2.849 to 3.811 gcm −3 . Correspondingly, the molar mass (M) increases, while the molar volume (V m ) decreases, indicating a more tightly packed glass matrix. The ion concentration increases (N) and related properties such as polaron radius (r p ) and interionic distance (r i ) decrease, further compacting the network and improving its structural integrity. The elastic moduli increase, as BaO/ZnO content increases. The shielding properties have been investigated from 0.122 to 0.678 MeV. The comparison of half value layer (HVL) with other shielding glasses confirms that Zn20Ba20 glass has good attenuation performance.
The need for high-performance oxide thin-film transistors that can be produced at low temperatures is growing due to the quick development of flexible electronics technology. High film defect density, poor electrical performance, and inadequate stability are common problems with traditional low-temperature techniques. To this end, this paper proposes and validates a novel dual-laser annealing strategy based on electron-phonon cooperative excitation, enabling the fabrication of high-performance In 2 O 3 thin-film crystals under a low thermal budget. This method employs an ultraviolet laser (355 nm) to induce surface melting and restructuring via an electronic excitation mechanism, combined with a mid-infrared laser (2.8 μm) to achieve selective in-phase oxygen vacancy repair through a phonon resonance mechanism. Results indicate that under a low thermal budget of 180 °C, the electrical performance of TFTs treated with dual-laser co-processing significantly improves: μ sat reaches 1.28 cm 2 V −1 s −1 , I on /I off increases to 1.20 × 10 7 , V th stabilized at 3.71 V, the subthreshold swing decreased to 1.05 V/dec, and the interfacial trap density was minimized. In bias stress testing, the device exhibited the highest stability, with threshold voltage drift significantly lower than that of devices without laser treatment or with single laser treatment. Furthermore, scanning electron microscopy (SEM) and X-ray photoelectron spectroscopy (XPS) were employed to systematically characterize the surface morphology and chemical state of the In 2 O 3 film, further verifying the film’s uniformity. The trade-off between defects and performance in low-temperature processes is thus effectively resolved by dual-laser annealing through the synergistic excitation of electrons and phonons, offering a novel method for the low-heat-budget, high-performance fabrication of flexible oxide electronic devices.
NASICON-type Na 3 V 2 (PO 4 ) 3 (NVP) is considered a promising cathode material for aqueous zinc-ion batteries due to its high operating voltage and substantial specific capacity. However, its practical application is significantly limited by poor electronic conductivity. To solve this problem, this paper introduces a carbon sphere framework supporting carbon-coated NVP (denoted as NVP-C@CSs). This composite was synthesized via a combination of hydrothermal and high-temperature calcination methods, which simultaneously improve conductivity and zinc storage capacity. The results indicate that the crystal structure of NVP remains intact after the introduction of CSs. Benefiting from the conductive CS framework, the NVP-C@CSs composite exhibits enhanced electronic conductivity (1.60 × 10 −4 vs 1.20 × 10 −4 S cm −1 ) and consequently superior electrochemical performance. At a low current density of 100 mA g −1 , the NVP-C@CSs composite delivers a discharge specific capacity of 126 mAh g −1 , higher than that of the NVP-C material (113 mAh g −1 ). The composite also exhibits excellent rate capability, with a capacity of 90 mAh g −1 at 2000 mA g −1 , significantly exceeding that of NVP-C (59 mAh g −1 ). This work provides an efficient approach to developing high-performance NVP composites for zinc-ion batteries.
The interfacial charge dynamics at the absorber/electron transport layer (ETL) interface critically influence the performance of perovskite solar cells (PSCs). Unfavorable interfacial properties can induce improper band alignment and mid-gap defect states, leading to enhanced charge-carrier recombination and reduced device efficiency. In this study, we employed SCAPS-1D to simulate a dual-electron transport layer (SnS2/WS2) integrated with a lead-free inorganic Ba3NCl3 absorber. The SnS2/WS2 bi-ETL promoted a spike-like band alignment with a small positive conduction band offset and favorable band bending at the WS2/Ba3NCl3 interface, effectively suppressing interfacial recombination and improving charge extraction. Device optimization was performed by systematically varying absorber and ETL thicknesses, as well as acceptor concentration (N-a) and defect density in the absorber. The optimized configuration, featuring a 1.1 mu m absorber thickness, N-A of 10(17) cm(-3), and defect density of 10(12) cm(-3), yielded a maximum power conversion efficiency (PCE) of 33.4%, with J(sc) of 38.37 mA & centerdot;cm(-2), V-oc of 1.02 V, and a fill factor of 85%. Furthermore, the effects of operating temperature (300-500 K) and absorber thickness on device performance and quantum efficiency were analyzed. These findings provide valuable insight into key parameters governing high-performance Ba3NCl3 heterojunction solar cells.
