Asynchronous Design for Precision-Scaleable Energy-Efficient LDPC Decoder

This paper presents a low-density parity-check (LDPC) decoder design that uses scalable-precision calculation (SPC) and asynchronous circuit techniques to reduce power consumption. The decoder configures the computation precision to minimize circuit-level switching necessary for given target biterror rate (FER). The asynchronous circuit approach guarantees the completion of each compute-and-forward phase at necessary voltage levels. The voltage level is scheduled to ensure completion of minimum necessary decoding iterations. The proposed scheme is studied for the specific application of IEEE 802.16e to reduce the power consumption at a given target FER. The proposed design is evaluated on Nangate 45nm library. The results show that the proposed asynchronous design results in 51% reduction in terms of power consumption compared with full-precision decoding mode.