This paper proposes an integer-forcing (IF) receiver for a multiple-input multiple-output (MIMO) system. Two low-complexity, soft demapping methods are introduced, which can provide approximate log-likelihood ratios (LLRs) for quadrature amplitude modulation (QAM) mapping in IF detectors. We compared the packet error rate (PER) performance and channel noise of the IF detector with those of zero-forcing (ZF) and minimum min square error (MMSE) detectors, as well as with a list sphere decoding, depth-first search (LSD-DFS) detector, in a 4×4 IID (independent identically distributed) MIMO channel with a 16-QAM modulation testbed. The required precision of the IF detector is reported in the conclusion.

Traditionally, in most colleges and universities, students in the Electrical and Computer Engineering department must take an Introduction to ECE course during their first year. During the 2020 COVID-19 pandemic, most colleges and universities switched from face-to-face courses to online learning, so faculty, administrators, and staff could work remotely and safely. At the height of the pandemic, online learning became a necessity for many institutions. Recognizing the need for online, real-world, hands-on experience for first year students, the ECE department at Utah Valley University created a student-centered and project-based course to introduce students to the fundamentals of ECE and familiarize them with basic tools and concepts such as MATLAB, circuit design, and micro-processing. This new course is organized around three important concepts: 1) creating enjoyable and interesting projects for students, 2) connecting with real-world projects, 3) and acquiring online hands-on experience for the COVID-19 era. In this paper, we focus on the importance of offering an engaging ECE course and report on the successes of our Utah Valley University course, while considering the challenges for online education and the need to adapt to a post-COVID-era curriculum. Index Terms-introductory course; electrical and computer engineering, COVID-19, project-based, hands-on

The ability for governing bodies to provide aid quickly and accurately has been proven critical in preserving human lives [2]. In many disaster scenarios, such as high magnitude earthquakes or tsunamis, existing communication infrastructure could be rendered inoperable. This creates the need for additional disaster relief solutions. The most optimum solution to this issue is a long-range, batter-powered sensor network which could be deployed quickly and easily. This paper comprises the creation of a more efficient and accessible sensor network for use in situations which demand flexibility, such as in disaster relief.

A DNA computer requires DNA processor. A fundamental component of the processor is an arithmetic logic unit (ALU). The ALU performs all arithmetic operations in binary format, and the most critical operation is two's complement addition, which can involve addition, subtraction, multiplication, and division. Two's complement adders can be synthesized using multiple full adders. In this paper, a noise-resistant DNA computing full adder circuit is presented. The proposed adder circuit, unlike other circuits, takes strands as inputs and produces the results in the form of DNA strands. This is an important characteristic, since it enables multiple-level design. In addition, since all possible hybridization in this circuit is desired, it can control an abundance of unwanted strands. As a result, the synthesized adder is noise-resistant. While other multi-level designs might be possible (e.g., Nor-Nor design), the proposed design implements the full adder circuit as an integrated gate. The benefit of having an integrated circuit is that it eliminates the need for separate suppressors and activators. Before synthesizing the adder, we implemented AND, OR, and inverter gates and then extended these basic components to implement the desired circuit. The proposed designs were implemented and tested using Visual DSD programming and simulation tool.

In this paper we introduce the algorithm and the fixed point hardware to calculate the normalized singular value decomposition of a non-symmetric matrices using Givens fast (approximate) rotations. This algorithm only uses the basic combinational logic modules such as adders, multiplexers, encoders, Barrel shifters (B-shifters), and comparators and does not use any lookup table. This method in fact combines the iterative properties of singular value decomposition method and CORDIC method in one single iteration. The introduced architecture is a systolic architecture that uses two different types of processors, diagonal and non-diagonal processors. The diagonal processor calculates, transmits and applies the horizontal and vertical rotations, while the non-diagonal processor uses a fully combinational architecture to receive, and apply the rotations. The diagonal processor uses priority encoders, Barrel shifters, and comparators to calculate the rotation angles. Both processors use a series of adders to apply the rotation angles. The design presented in this work provides $2.83\sim649$ times better energy per matrix performance compared to the state of the art designs. This performance achieved without the employment of pipelining; a better performance advantage is expected to be achieved employing pipelining.

This paper presents a novel asynchronous design approach for multiple input multiple output (MIMO) satellite communication (SatCom) systems. One of the main challenges for MIMO SatCom systems is that these are prone to transient faults that typically are attributable to radiation hazards. Hence, instead of using conventional synchronous circuits, we conceive our design using asynchronous circuits since it inherently has a high tolerance to transient fault. Additionally, we adopt accelerated dual paths (ADP) design into our system. By carefully arranging the data flow between the two paths, the ADP design approach can help to further accelerate the asynchronous system and increase the reliability of the system by circumventing transient faults induced delay, as well as tolerating latch-ups and other permanent faults. The numerical results show that this design approach provides promising results. For example, the proposed design can decrease the delay overhead of the entire system from 43.5 to 19.8 % at the fault rate of 400/clock cycle.

This paper presents an iterative soft decision based lattice reduction (LR) aided Schnorr-Euchner (SE) multiple-input-multiple-output (MIMO) decoding algorithm, which reduces the gap in performance between suboptimal K-best and maximum likelihood (ML) detectors. Following IEEE 802.16e standard, we develop an iterative soft decoding algorithm for 4×4 MIMO with different modulation schemes. Using this method, we obtain 1.1 to 2.7 dB improvement over iterative soft decision based least sphere decoding (LSD) for different iterations. Then, using extensive simulation, we determine the optimum values for list size and saturation limit, which are the two governing parameters of our algorithm. Finally, we demonstrate that limiting the log likelihood ratio (LLR) values in LR-aided and LSD algorithm results in more than 8x reduction in list size as well as in the complexity of detectors and LLR calculation units.

This paper presents a very-large-scale integration (VLSI) design to reconstruct compressively sensed data. The proposed digital design recovers signal compressed by specific analog-to-digital converter (ADC). Our design is based on a modified iterative hard threshold (IHT) reconstruction algorithm to adapt unknown and varying degree of sparsity of the signal. The algorithm is composed empirically and implemented in a hardware-friendly fashion. The reconstruction fidelity using fixed-point hardware model is analyzed. The design is synthesized using Synopsys Design Compiler with TSMC 45nm standard cell library. The post-synthesis implementation consumes 165 mW and is able to reconstruct data with information sparsity of 4%, at equivalent sampling rate of 1 gigasample-per-second (GSPS).

This paper presents an iterative soft decision based adaptive K-best multiple-input-multiple-output (MIMO) decoding algorithm. It has the flexibility of changing the list size, K with respect to the channel condition, although the accurate measurement of signal to noise ratio (SNR) is not required. Moreover, the concept of iterative soft decision based lattice reduction (LR)-aided minimum mean square error (MMSE) extended K-best decoder is applied instead of conventional hard decision based K-best algorithm to reduce computational complexity to a great extent It is found that the ratio of the minimum path metric to the second minimum can provide reliable estimation of channel condition. Hence, in the proposed algorithm, K is changed adaptively with respect to the ratio. Using this method with less number of K, we can obtain similar performance compared to the conventional LR-aided K-best algorithm operating with maximum list size of 64. Comparing to the fourth iteration of iterative soft decision based least sphere decoding (LSD), the proposed method with less K achieves 1.6 dB improvement at the bit error rate (BER) of 10 -6 . Therefore, similar performance can be obtained by the proposed adaptive K-best algorithm with less computational complexity of the tree search decoder.

For this study, we designed and optimized a two-level thermoelectric pavement energy harvesting system. The optimization was evaluated based on the cost per unit of energy ($/J) as the target function. The idea behind the two-level thermoelectric system is to use thermoelectric power generator (TEG) modules on different depths of pavement to maximize the heat exchange efficiency of temperature gradients created by both daytime and night-time conditions. As the temperature difference is the driving force for the flow of thermal energy through the TEG, and the TEG turns a certain percentage of thermal energy into electrical energy, the two extrema created by daytime and night-time temperatures have the most potential to generate electricity. Since the generated energy is entirely dependent on the temperature profile and thermal exchange between different elements of the device, and between the device and the environment below the surface, we had to develop tools to provide an accurate analysis of these exchanges. In addition, we created an accurate temperature profile by extrapolating from existing geological information. We calculated the associated costs and changes in total generated energy for each change in the design parameters using our evaluation model and determined their effect on the target function.

Manufacturing and operation of wireless systems require a practical solution for achieving low-power and high-performance when using advance communication apparatus such as that using multiple-input and multiple-output (MIMO). Often algorithm solutions achieve very high performance but over only in a narrow range of operating parameters. This paper presents a hardware design of MIMO detection that allows real-time switching between various algorithms and detection effort to achieve high performance over the wide-range of signal to noise ratio (SNR) found in realistic operating conditions. We illustrate a design with over 80% reduction in detection power that satisfies the required quality of service (QoS) in SNRs (Eb/No) as low as 8.7 dB.

The challenges in satellite communication (SatCom) include but not limited to the customary complications of telecommunication such as channel condition, signal to noise ratio (SNR), etc. SatCom system is also prone to transient and permanent radiations hazards. Hence, in spite of the harsh environmental factors (weather phenomena, solar events, etc), a SatCom system must maintain reliable and predictable communication functions with limited source of power. This paper presents a SatCom system design for achieving both low-power and high fidelity communication. The design uses cooperative multiple input multiple output (MIMO) for spectral efficiency and diversity, low-density parity-check (LDPC) decoding for near Shannon-limit gain, and dynamic voltage and frequency scaling (DVFS)-assisted asynchronous circuit designs to achieve low-power and fault tolerance. The MIMO system permits uninterrupted service in the event of temporary/permanent link or unit failures. The results show that the resilience against injected radiation levels of upto about 25 fempto-Coulombs on critical path is achieved. This is more than 600 times the minimum charge required to logically flip a gate output in ordinary static CMOS gate.

This paper presents a low-density parity-check (LDPC) decoder design that uses scalable-precision calculation (SPC) and asynchronous circuit techniques to reduce power consumption. The decoder configures the computation precision to minimize circuit-level switching necessary for given target biterror rate (FER). The asynchronous circuit approach guarantees the completion of each compute-and-forward phase at necessary voltage levels. The voltage level is scheduled to ensure completion of minimum necessary decoding iterations. The proposed scheme is studied for the specific application of IEEE 802.16e to reduce the power consumption at a given target FER. The proposed design is evaluated on Nangate 45nm library. The results show that the proposed asynchronous design results in 51% reduction in terms of power consumption compared with full-precision decoding mode.

Drowsiness presents major safety concerns for tasks that require long periods of focus and alertness. While there is a body of work on drowsiness detection using EEG signals in neuroscience and engineering, there exist unanswered questions pertaining to the best mechanisms to use for detecting drowsiness. Targeting a range of practical safety-awareness applications, this study adopts a machine learning based approach to build support vector machine (SVM) classifiers to distinguish between awake and drowsy states. While broadband alpha, beta, delta, and theta waves are often used as features in the existing work, lack of widely agreed precise definitions of such broadband signals and difficulty in accounting for interpersonal variability has led to poor classification performance as demonstrated in this study. Furthermore, the transition from wakefulness to drowsiness and deeper sleep stages is a complex multifaceted process. The richness of this process calls for inclusion of sub-band features for more accurate drowsiness detection. To shed light on the effectiveness of sub-banding, we quantitatively compare the performances of a large set of SVM classifiers trained upon a varying number of 1Hz sub band features. More importantly, we identify a compact set of neuroscientifcally motivated EEG features and demonstrate that the resulting classifier not only outperforms traditional broadband based classifiers but also is on a par with or superior than the best sub-band classifiers found by thorough search in a large space of 1Hz sub band features.

IEEE 802.22, also called Wireless Regional Area Network (WRAN), is the newest wireless standard being developed for remote and rural areas. In this paper an overview of the standard, and more specifically its PHY layer is introduced. In order to evaluate the performance of the system, we model the PHY layer in MATLAB/SIMULINK and extract the Bit Error Rate (BER) of the system for different code rates and modulation schemes with noisy channel.

In this paper, we present a floating-point model for OFDM part of the IEEE 802.16a standard. This part has been assigned as the mandatory structure for WiMax. Next, we present a bit-true model for Viterbi decoder and encoder of it with the constraint of having less than 0.5 dB degradation in the performance of the system while minimizing the hardware cost of it. Since the most sensitive modulation in the standard is 64QAM with the rate 5/6 for convolution coding, it has been used for bit-true modeling. While all of the system blocks are floating-point, we have extracted the BER of the ideal system under different channel noises with random binary input data and AWGN noise. We have validated our model by comparing its results with those of analytical formulas which are driven for AWGN channel noise. We have developed the bit-true model of the Viterbi block and have tuned the system to satisfy all of the standard requirements and the condition of less than 0.5 dB degradation in the performance at the worst case. This 0.5 dB condition is used in many papers as the implementation marginal value. Finally, the bit-true parameters of this experience can be used for different hardware realization structures (fixed-point or floating-point). Also samples of the input and output data of each block in the bit-true model can be used as a test bench for the same hardware structure. The final Viterbi decoder designed with traceback depth equal to 50 and 8 bit soft decision.

A report is made on one of the issues first observed when using a block-floating-point system in a time equaliser of an ADSL modem. It is believed that, until now, this important phenomenon has been neglected by researchers. It is shown that neglecting this issue may increase the round-off error significantly. Two solutions to improve performance are proposed.

In recent years, several implementations have been reported for Digital Audio Broadcasting (DAB) systems. Normally, implementation parameters of these systems are extracted from extensive system level simulations to adjust various parameters while maintaining the required performance. In this paper, the bit-true model of a DAB system is extracted and an accurate model simulation for the system is performed to find the word lengths of various parameters to approach the best trade off between performance and hardware cost. Here, the decimation-in-time algorithm for FFT/IFFT and adaptive LMS algorithm for time equalizer is adopted.