Design and Analysis of Sub-Threshold Level Shifter for Very High Speed and Ultra-Low Power Applications

In this paper, we propose a robust level shifter based on a cascode current mirror operating at low voltage, a diode-connected stack of PMOS and NMOS diodes driving the output buffer of split input type. Diode connected stack has helped in achieving a reduced swing in voltage at the input of the output buffer. This helps in achieving reduced static power dissipation. Experimental results across various corners of operation ensure the efficiency of the proposed design in different functional modes. With an average propagation delay of 8.565 ns and an incredibly low power consumption of 0.427 nW, the design enables the voltage up conversion of a 300 mV, 1 MHz input rectangular pulse to 1.2 V exclusively for 45 nm CMOS technology node. The proposed level shifter consumes a silicon area of 41.4225 & micro;m2. For the 90 nm CMOS technology node, it has an average propagation delay of 9.04 ns and an incredibly low power consumption of 76.02 nW. The design enables the voltage up conversion of a 400 mV, 100 kHz input rectangular pulse to 0.9. The proposed circuit allows up conversion of 0.4 V to 1.8 V at a nominal delay of 75.38 ns and static power consumption of 0.165 nW at 180 nm CMOS technology node, which is quite less as compared to the reported circuit.