Multi-valued logic (MVL) offers a promising alternative to binary logic, enhancing data processing efficiency within the same transistor constraints. Graphene nano-ribbon field effect transistors (GNRFETs) demonstrate strong potential for MVL applications due to their high operational frequency and unique electronic properties. In this work, we present the design and implementation of ternary full adder and full subtractor circuits optimised for arithmetic logic units (ALUs). Additionally, we redesigned comparable circuits using carbon nano-tube field effect transistors (CNTFETs) to evaluate performance differences. Our comparative analysis highlights distinct advantages and trade-offs between GNRFET and CNTFET architectures. GNRFET-based designs achieved a peak performance of 10 GHz, significantly surpassing the minimum operational frequency of 0.5 GHz observed in CNTFET-based counterparts. However, the power dissipation of GNRFET circuits was about 27% to 28.5% of that in CNTFET designs, while exhibiting about 158% decrease in processing speed. These findings underscore GNRFET's viability for MVL applications, particularly in high-speed computational environments.
The widespread adoption of solar-powered Electric Vehicles (EVs) is hindered by inherent limitations of photovoltaic (PV) systems, which generate low and highly fluctuating output voltages under varying irradiance conditions. Conventional converters often fail to deliver the required high voltage gain with minimal losses, as they suffer from issues such as high ripple content, reduced efficiency and bulky designs that limit their practicality for EV applications. This research introduces an innovative solar-powered Electric Vehicle (EV) drive system that combines a novel High-Gain Improved Quasi-Coupled Inductor Boost (IQCIB) Converter with an adaptive Secretary Bird Optimised Proportional-Integral (SBO-PI) controller. Unlike conventional converters, the IQCIB topology achieves high voltage gain with reduced ripple and minimised energy losses through enhanced magnetic coupling, enabling efficient elevation of the low PV output voltage for EV applications. The SBO-PI controller further distinguishes the system by dynamically adjusting control parameters in real time, ensuring adaptability to fluctuating solar irradiance and varying load demands. Integrated on a DC bus framework, the proposed architecture facilitates uninterrupted energy flow between the PV array, battery and motor, achieving remarkable 96.2% conversion efficiency. By combining these innovations, the system significantly improves EV range, reliability and sustainability, representing a vital advancement towards autonomous green transportation solutions.
Hybrid energy renewable systems (HERS) employ a dedicated interfacing power electronic converter for individual sources. With an increase in the number of sources, the number of interfacing converters, semiconductor switches, diodes, and passive elements (inductor and capacitor) also increases. As a result, the overall cost, volume, and losses will increase. Therefore, a multiport converter (MPC) is proposed in this paper to integrate multiple sources, a battery energy storage system (BESS), and a load with less component count. The proposed single-inductor MPC has multiple input ports, an output port, and one bidirectional port. The proposed configuration minimises the number of components, thereby reducing losses and improving converter efficiency. The MPC operates in boost, buck, and buck - boost modes with three different battery operating cases, such as idle, charging, and discharging. This allows the proposed MPC to have flexible modes of operation, which include individual or simultaneous input sources supplying the load as well as charging the battery. The mathematical analysis is carried out to derive the steady-state equations for detailed analysis of efficiency, power losses, and device stresses under various operating scenarios. The experimental results validate the operation of the proposed MPC in different modes. The comparative analysis proves the superiority of the proposed MPC in comparison with the reported similar works.
The direction of arrival (DOA) estimation is an important research problem widely investigated in the literature. Several methods have been proposed for the solution of this problem earlier. One group of the DOA estimation methods is subspace optimisation methods such as MUSIC, ESPRIT and Matrix Pencil method. Also, antenna array configuration plays an essential role in direction finding applications. In this paper, a new DOA estimation approach has been proposed which uses a uniform linear array (ULA). The inter-element spacings and excitation amplitudes of ULA have been optimised using differential evolution algorithm for the estimation of the angles of incidence. It has been shown that a significant advantage has been obtained by merging the Matrix Pencil method with the differential evolution algorithm. The effects of several parameters (noise level, the number of signal sources, the number of antenna elements, angle of incidence) have been investigated. The results have been discussed and have been compared with the literature. The simulations indicate that the suggested approach offers substantial benefits compared to conventional techniques, particularly regarding precision in challenging situations.
This paper presents a high-performance, triangular split-ring resonator (TSRR) metamaterial-inspired MIMO antenna with triple-band and dual-polarisation, designed for modern wireless applications, including 3 G, 5 G, and 6 G. The antenna operates in three distinct frequency bands: 1950-2100 MHz, 3.2-4.3 GHz, and 8.0-8.3 GHz, covering 3 G, 5 G (sub-6 GHz), and beyond 5 G (potential 6 G bands). The design evolves systematically from a single TSRR-based antenna element to two, three, and four-element MIMO configurations, effectively addressing the challenge of mutual coupling. A rectangular split-ring structure between the antennas improves isolation by up to -20 dB between the elements. Measurement results show excellent MIMO performance, with input reflection coefficients (S11, S22, S33 and S44) <-10 dB, isolation (S21, S31, S41) <-20 dB, envelope correlation coefficient (ECC) <0.04, channel capacity loss (CCL) = 0.4 bits/sec/Hz, and diversity gain (DG) = 10. This antenna design is a promising solution for future wireless communication systems.
Accurate estimation of the state of charge (SOC) is essential for the safety and efficient operation of lithium-ion batteries (LIBs). However, the accuracy of integer-order model for SOC estimation is poor. In this work, the fractional-order RC model (FOM-RC) is used to identify the model parameters including polarisation resistance, fractional-order capacitance and the order. Subsequently, the terminal voltage and SOC are calculated in MATLAB/Simulink by the fractional-order integrator and fractional-order extended Kalman filter (FOEKF), respectively. Then the accuracy of SOC estimation performance is discussed in Case 1 (dynamic stress test, DST) and Case 2 (federal urban driving schedule, FUDS). Finally, the mean absolute error (MAE) and root mean square error (RMSE) of the SOC estimation by FOEKF is discussed and compared with those by the extended Kalman filter, unscented Kalman filter and cubature Kalman filter (CKF). The results indicate that FOEKF offers higher accuracy of SOC estimation, respectively reducing the MAE and RMSE by 17.53% and 14.78% in Case 1, and by 31.40% and 34.31% in Case 2 compared with CKF.
Digital image processing relies heavily on adders and multipliers, particularly in error-tolerant applications. Approximate multipliers enable efficient deployment on embedded processors under power budgets. In this paper, an efficient design of approximate hybrid multiplier architecture namely HBDM (Hybrid Booth and Decoder Logic-Based Multiplier) is proposed by considering Radix-16 Booth algorithm and Decoder Logic-based multiplier. This work aims to simplify the accumulation stage by effectively minimising partial product rows. In the proposed design, most significant half bit of multiplier is used for radix-16 booth encoding and remaining least significant half bits are used for decoder logic-based multiplier. Moreover, hybrid adder is used in the sub-modules to minimise area and energy while preserving respectable accuracy levels. Four distinct configurations (HBDM-1/2/3/4) in sub-modules are further suggested and analysed. Synthesis results on Cadence Genus tool shows that proposed 8 & times; 8 inaccurate multiplier design minimise design complexity with balance trade-off between power and accuracy. Proposed HBDM-4 design exhibits 47.29% reduction in energy compared to unsigned radix-16 booth multiplier with MRED of 0.0173. The effectiveness of proposed multiplier in image processing applications is evaluated. The findings demonstrate that the suggested approximate multiplier has PSNR above 30 dB and SSIM is closer to 1.
This article introduces an eight-port wideband Multiple-Input Multiple-Output (MIMO) antenna with suppressed mutual coupling for radar systems and satellite communications. To reduce inter-element coupling, the design incorporates a neutralisation line and a defected ground structure (DGS) to enhance isolation and minimise mutual coupling to >30 dB, ensuring efficient MIMO operation for high-frequency communication systems. The fabricated antenna has dimensions of 40 & times; 58 & times; 0.8 mm(3) (6.07 lambda g & times; 8.80 lambda g & times; 0.121 lambda g at 36 GHz) The printed antenna achieves a wide bandwidth from 27 to 45 GHz and gain of 10.5 dBi. The diversity parameter analysis reveals an envelope correlation coefficient (ECC) <0.00025, a diversity gain (DG) >9.999 dB. This antenna's design manages to combine high isolation, large bandwidth, compact dimensions, and good MIMO diversity measurements. The observed outcomes closely match with those predicted by the simulation. Furthermore, the presented design obtains enhanced efficiency and increased compactness in comparison with current and more contemporary efforts. The proposed architecture addresses critical challenges such as strong mutual coupling in compact multi-port arrays, wideband impedance matching, stable radiation characteristics and high efficiency for radar and satellite communication systems.
In the pool of RSC MLI, T-type is one of the simplified topologies with an appreciable reduction in switch count and is most often reported with multi-reference (MR-PWM) and Reduced Carrier (RC-PWM) schemes. Though T-type is widely reported with various low-frequency and carrier frequency schemes, the novel modified reduced carrier (MRC) claims to produce superior line THD performance over the conventional MR and RC PWM schemes. However, the proposed work identifies that the harmonic performance of the MRC varies with the variation in carrier frequency and the obtained line THD is sufficiently good for the range of carrier frequencies (fcr) in triple-n multiples of the fundamental frequency (fs), i.e. fcr = Triple-n*fs. For non-triple multiples, i.e. fcr not equal Triple-n*fs, its line-harmonic performance is degraded. Elevating the above limitation of MRC, this paper proposes a merged carrier (MC) PWM that produces satisfactory and superior line-THD performance over the state-of-the-art reported for T-type at any range of carrier frequency (fcr). The performance of the proposed scheme on a three-phase T-type RSC-MLI is analysed for five-level and seven-level configurations under dynamic variations in load and modulation index (ma and mf) perturbations. The demonstrated simulation results are validated on a hardware prototype integrated with FPGA controller.
This article presents an optimised design of a Schmitt trigger buffer using DTMOS technology, aimed at achieving higher speed and lower noise margin. Two modified circuits are proposed: a noise-immune DTMOS Schmitt trigger that effectively suppresses noise and a high-speed DTMOS Schmitt trigger that operates with reduced power consumption. The key objectives of this work are to reduce transistor count, minimise power usage, decrease noise and delay, and lower switching current. DTMOS devices, capable of operating at low voltages and high speed, are particularly suitable for energy-efficient applications. In contrast, CMOS-based designs lead to increased power, delay, and noise. The noise-immune DTMOS circuit, which includes feedback, achieves a hysteresis width of 159 mV at 0.3 V, which increases to 254 mV at 0.5 V - enhancing its noise-filtering capability. The high-speed DTMOS circuit exhibits a narrow hysteresis width of 6 mV, switching ON at 1.2 V and OFF at 1 V, indicating fast operation. Both circuits demonstrate efficient low-voltage performance, highlighting DTMOS as a superior alternative to CMOS for low-power, high-speed digital applications. The design is implemented in 90 nm technology using the cadence virtuoso tool and operates at a low supply voltage of 0.3 V.
In this paper, we propose a robust level shifter based on a cascode current mirror operating at low voltage, a diode-connected stack of PMOS and NMOS diodes driving the output buffer of split input type. Diode connected stack has helped in achieving a reduced swing in voltage at the input of the output buffer. This helps in achieving reduced static power dissipation. Experimental results across various corners of operation ensure the efficiency of the proposed design in different functional modes. With an average propagation delay of 8.565 ns and an incredibly low power consumption of 0.427 nW, the design enables the voltage up conversion of a 300 mV, 1 MHz input rectangular pulse to 1.2 V exclusively for 45 nm CMOS technology node. The proposed level shifter consumes a silicon area of 41.4225 & micro;m2. For the 90 nm CMOS technology node, it has an average propagation delay of 9.04 ns and an incredibly low power consumption of 76.02 nW. The design enables the voltage up conversion of a 400 mV, 100 kHz input rectangular pulse to 0.9. The proposed circuit allows up conversion of 0.4 V to 1.8 V at a nominal delay of 75.38 ns and static power consumption of 0.165 nW at 180 nm CMOS technology node, which is quite less as compared to the reported circuit.
A miniaturised dual-band circularly polarised (circular polarization) equilateral triangular monopole radiator for mid sub-6 GHz 5G G/WLAN operations is presented in this manuscript. The developed design comprises a planar microstrip equilateral triangular patch (T-patch) simultaneously loaded with O-shaped slot (OSS) and multiple-asymmetric rectangular slots (R-slots) at the centre and different locations of the radiator to enhance conventional T-patch performances. A pair of I-shaped slots (ISS) protracted degraded ground structure (DGS) to perturb the current distribution on the DGS and inverted H-shaped strip (IHSS) to accomplish dual-excitation mode and widening the impedance bandwidth (IBW). The calculation method and the attractive tri-group of orthogonal rectangular slots (ORS) to generate multiple bands and CP constitute the principal novelty of this study. The proposed design is configured on a thin lossless Rogers4003C material of volume 30.67 & times; 34 & times; 1.524 $m{m<^>3}$mm3. The measured performances show that the proposed manufactured radiator exhibits IBW of $37.74\% $37.74% and $18.34\% $18.34%, peak gain of 2.137 and 5.10 dB at 4.246 and 5.9426 GHz, respectively, axial ratio (AR) of 1.859 dB and simulated 3-dB axial ratio bandwidth (ARBW) of $3.25\% $3.25% at the upper operating frequency band (OFB). This antenna is suitable for wireless 5G application mobile phone and WLAN communication systems.
This study presents a non-isolated, high-gain multi-input DC-DC converter designed specifically for the seamless integration of hybrid energy sources. The architecture uses a common-ground (CG) layout between the input sources and the load, which simplifies gate drive needs and mitigates electromagnetic interference. A thorough steady-state analysis is carried out to generate the voltage gain expression and evaluate the voltage and current stresses on semiconductor and passive components. To improve dynamic response, a small-signal state-space model is used to create a proportional-integral-derivative (PID) controller. The design's performance is experimentally tested using a 100-watt laboratory prototype. Thermal and efficiency assessments ensure the system's dependability and operating efficacy. Notable features include continuous input current (CIC) from many sources, stable operation across a large duty ratio $\left(D ight)$D range, and a simplified switching method, making the suggested architecture appropriate for high-voltage renewable energy applications.
In this paper, a compact ultra-wideband (UWB) dual-port MIMO dielectric resonator antenna (DRA) with defected ground plane is proposed for on-body wireless body area network (WBAN) applications. The antenna employs a U-shaped dielectric resonator, two microstrip feeds, and parasitic strips to achieve wide impedance bandwidth and enhanced port isolation. Results reveal that wider and longer slots significantly improve impedance matching and inter-port isolation, while increasing slot depth in the dielectric enhances bandwidth and reduces coupling by suppressing surface currents. The fabricated prototype was experimentally validated on both rectangular and cylindrical tissue phantoms, as well as on animal tissue, demonstrating good agreement with simulations. The proposed antenna covers the UWB frequency range of 3.1-10.6 GHz with return loss below -10 dB and mutual coupling below -20 dB across the band. Furthermore, radiation analysis confirms broadside coverage with opposite phases for dual ports, ensuring reduced fading and improved channel capacity. The results confirm that the proposed antenna is robust for wearable and biomedical IoT devices requiring high data rates, low power consumption, and reliable UWB MIMO communication.
Among commercially available multilevel inverters, the cascaded H-bridge is widely adopted due to its modular structure and use of low-voltage, mature technology switching devices. A CHB fed by conventional level-shifted PWM offers improved harmonic performance but lacks inherent power-balancing capability among the sources, while phase-shifted PWM facilitates power balancing at the expense of higher switching losses. This paper presents a simplified single-carrier-based dual-modulation technique for a five-level CHB MLI that addresses these limitations. Notably, power balancing between the two DC sources of a CHB module is achieved within a single carrier cycle, which is significantly faster than existing methods that typically require one or more fundamental cycles. Uniform power sharing among the sources extends their lifespan. Moreover, the uniform thermal stress distribution among devices facilitates improved thermal management system design.Furthermore, the proposed technique shifts dominant output voltage harmonics to twice the carrier frequency, thereby improving the harmonic profile and reducing the required output filter size by approximately 50% compared to conventional level-shifted PWM.Extensive simulations and hardware validation confirm the effectiveness of the proposed PWM technique, and comparative analysis demonstrates its superiority over well-established methods.
