Design and Implementation of Power Management Integrated Circuit for Next-Generation SoCs with Energy Optimization and Thermal Protection in SCL-180 Nm CMOS Technology

The current study emphasises the schematic-level design and mixed-signal system-level validation of an innovative PMIC architecture developed using the Semiconductor Laboratory (SCL) 180 nm CMOS manufacturing technology. The suggested architecture incorporates a thorough multi-level approach to energy optimisation to address the particular constraints of engineering power blocks on a single chip for advanced SoCs. The architecture has a transistor-level Current-Mode Bandgap Reference (CMBGR), six channel Low Dropout Regulators (LDOs), and an incorporated thermal shutdown block. It also has behaviourally modelled Switched Mode Power Supplies (SMPS) that include Synchronous Buck and Boost regulators. The pre-layout schematic simulations show that the suggested CMBGR architecture gives a very stable 1.2 V reference with a temperature coefficient of 0.36 ppm/°C in an industrial temperature range from − 40 °C to 125 °C. The PSRR is 154 dB. The six LDO channels each give a regulated output of 1.8 V, with a dropout voltage of 500 mV and a PSRR of 66 dB. The synchronous Buck converters, whose designs were tested with verilog-A behavioural models, allow DVFS for the CPU core, several conventional DDR memory, and I/O voltage levels that can be changed. The built-in TSD block makes sure that the system shuts down safely at 150 °C.