One of the most deadly types of cancer that impact women worldwide is breast cancer (BC). Ultrasonography and mammography are two common ways to screen for breast cancer. One of the main shortcomings of existing methods is their incapacity to distinguish between benign and malignant cancer. It is a crucial diagnostic tool for BC diagnosis because the histopathology-based classification of breast cancer is based on histological images of BC. The article presents a novel deep learning approach for creating a multi-class BC classification model. The study’s dataset came from databases that are open to the public. Additionally, the histopathology images were subjected using Improved Anisotropic Filtering (IAF) in order to minimize noise. The model tumor region is segmented using a Modified Deep-View Fuzzy C-Means Clustering (MDV-FCMC) technique to increase its flexibility. Important features were then extracted using the Discrete Wavelet Hadamard Transform (DW-HT) and the Grey Level Co-occurrence Matrix (GLCM). The feature dimensionality problems must then be resolved. The method known as Enhanced Pufferfish Optimization (EPO) is used to choose the best features. To categorize the multi-class BC illness, the Channel-Spatial Attention based Convolutional Capsule Network (CSA-CCN) is presented based on these chosen features. Lastly, to improve the classifier model’s effectiveness, the Honey Badger Optimization (HBO) technique is used. With classification accuracy of 97.99
The Multiply and Accumulate (MAC) unit is a dynamic constituent in signal processing, cryptography and quantum computing, with low power and high speed is the necessary design. Conventional MAC units are implemented via irreversible logics that ultilizes high power resultant in information loss. To beat this limit, this paper contributes a Reversible Vedic Multiplier–Accumulator (RVMAC) that integrates the Vedic (Urdhva Tiryakbhyam) method with reversible logic to construct an energy-optimal arithmetic hardware. The unify Reversible Carry Save Adder (RCSA) is engage in the framework for partial product summation and accumulation, which provides less delay and high-speed functioning with less information loss. Designed in a ranked order from a 2-bit multiplier block, that scalable upto 4-bit, 16-bit, 32 bit so on, which enables optimal quantum cost, garbage outputs and constant inputs. The entire framework is designed and implemented in Xilinx Artix-7 FPGA. The synthesized report shows that speed of the proposed Reversible Vedic Multiplier–Accumulator (RVMAC) architecture is improved by 37.98
The current study emphasises the schematic-level design and mixed-signal system-level validation of an innovative PMIC architecture developed using the Semiconductor Laboratory (SCL) 180 nm CMOS manufacturing technology. The suggested architecture incorporates a thorough multi-level approach to energy optimisation to address the particular constraints of engineering power blocks on a single chip for advanced SoCs. The architecture has a transistor-level Current-Mode Bandgap Reference (CMBGR), six channel Low Dropout Regulators (LDOs), and an incorporated thermal shutdown block. It also has behaviourally modelled Switched Mode Power Supplies (SMPS) that include Synchronous Buck and Boost regulators. The pre-layout schematic simulations show that the suggested CMBGR architecture gives a very stable 1.2 V reference with a temperature coefficient of 0.36 ppm/°C in an industrial temperature range from − 40 °C to 125 °C. The PSRR is 154 dB. The six LDO channels each give a regulated output of 1.8 V, with a dropout voltage of 500 mV and a PSRR of 66 dB. The synchronous Buck converters, whose designs were tested with verilog-A behavioural models, allow DVFS for the CPU core, several conventional DDR memory, and I/O voltage levels that can be changed. The built-in TSD block makes sure that the system shuts down safely at 150 °C.
In this paper, different (diffusion, flicker, and generation recombination (G-R)) noises are studied and analyzed for triple material gate (TMG), double material gate (DMG) and single material gate (SMG) step FinFET devices and compared their performances in terms of ON current, OFF current, threshold voltage (Vth), subthreshold swing (SS), and analog/RF performance. Using suitable gate material improves the SS, ION, and ION/OFF characteristics in the presence of noise. The drain current noise spectral density (Sid) performance is measured and studied for all structures and compared to other existing devices. It is observed that the TMG step FinFET device has an improved Sid value of 4.60*10–15 A2/Hz performance in the presence of G-R noise. Moreover, this dissertation also reported that TMG step FinFET device with flicker noise is noticed to be significant to obtained peak values of analog/RF parameters such as transconductance (Gm) of 11.74 mS, transconductance generation factor (TGF) 35.11 V−1, transconductance frequency product (TFP) of 290 THz/V, and cut-off frequency (Ft) of 33.84 GHz respectively.
In recent years, the capacity of inverse filters (IFs) to reconstruct a distorted signal has led to an increase in their employment as a signal conditioning circuit in analogue signal processing. In this research, a novel method for operating an inverse filter of third order is presented. Using a single Operational Transresistance Amplifier (OTRA) and some passive components, the third order inverse low pass filter (ILPF), inverse high pass filter (IHPF), and inverse band pass filter (IBPF) have all been realised in this study. The suggested third order inverse filters outperform existing second order inverse filters reported in various literatures by 33.15
The effects of 3 MeV electron radiation on the electrical performance of commercial 650 V silicon carbide (SiC) MOSFETs are investigated at doses of 50 kGy, 100 kGy, and 200 kGy. Post-irradiation results reveal a reduction in on-state resistance, indicated by increased drain current (IDS), and a negative shift in threshold voltage (VTH) due to positive charge trapping in the gate oxide. At higher doses, VTH stabilizes as electron injection neutralizes positive traps. Capacitance and gate-source leakage current analyses show radiation-induced defect formation, with Fowler–Nordheim (FN) tunneling identified as the dominant leakage mechanism. These findings advance the understanding of SiC MOSFET degradation under radiation, contributing to developing robust power devices for space and radiation-critical applications.
The increasing development of portable and power-sensitive devices has raised the need for high-performance and energy-efficient circuits, especially in image processing applications that deal with huge datasets and require a substantial amount of resources. CMOS technology makes conventional digital multipliers and adders, which are made for precise calculations, more compact, but they still often have large leakage currents and high power consumption. FinFET technology tackles many of these issues by reducing leakage power and providing greater control over short-channel effects. Even FinFET-based accurate arithmetic units struggle to strike a balance between computational accuracy and energy efficacy in applications that allow for some error tolerance. This article focuses on designing a low-power approximate multiplier based on Gate Diffusion Input (GDI) compressors (LAMGDIC) FinFET technology, specifically to tackle image denoising. The approximate design uses XNOR-GDI compressors, which allow the implementation of controlled approximations by simplifying certain bit positions to gain an advantage in power decrease at the expense of some accuracy when performing the computations. This approach reduces transistor count, switching activity, and leakage power, which are crucial for low-energy operation. The proposed multiplier has been integrated into a Gaussian kernel filter, a common image denoising technique, to demonstrate its effectiveness. The proposed method achieves 7.8125 × 10− 05 of NMED, 0.0103 of MRED, 0.2300 μ W of power, 0.0480ns of delay, and 0.0110fJ of PDP. The LAMGDIC-based approximate multiplier in FinFET technology offers a better trade-off among accuracy and energy to be used for image denoising due to its reduced transistor count, low leakage, and better power, delay, and PDP.
The demand for high-performance hardware accelerators is growing, which are widely used nowadays for implementation of Deep Learning methods like that of Convolutional Neural Networks (ConvNet / CNN) on reconfigurable devices. The Multiply-Accumulate (MAC) units are the warhorses behind the remarkable speed and efficiency of convolution operations. Double MAC approach combines two units of MAC operations into a single Digital Signal Processing module of a reconfigurable Field Programmable Gate Arrays (FPGA), thereby increasing the throughput of Convolutional Neural Network accelerators. By dynamically adjusting the precision of MAC operations to 4-bit, 8-bit, and 16- bit fixed and floating-point representations, MAC units can be optimized for efficient resource utilization and power consumption. In this paper, a Double multiply-accumulate unit, dynamically changing precision with 8-bit and 16-bit, is proposed. By leveraging the inherent parallelism and pipelining capabilities of Field Programmable Gate Arrays (FPGA), Double multiply-accumulate approach optimizes the utilization of hardware resources while minimizing the power consumption. The flexible precision scaling in the proposed work proves advantageous in convolution layers, where greater precision is required for final classification and smaller precision in initial stage. Simulation, Synthesis and FPGA Implementation of the proposed Double MAC unit with dynamic precision scaling have been done and it is found successful. The proposed Double MAC approach has showed twofold improvement in throughput and 15
This work proposes a high-performance Current-Starved Negative-Skewed Voltage-Controlled Oscillator (CSNS-VCO) with design optimization targeted at wideband frequency synthesis in advanced CMOS technologies. Classic ring-oscillator VCOs suffer from limited delay controllability, weak voltage-to-frequency gain, and reduced oscillation amplitude under nanoscale supply and device variations. The proposed topology utilizes a hybrid delay-cell architecture that integrates current-starved inverting stages with a negative-skewed feedback path to augment the effective transconductance and reduce transition time. By redistributing the charging and discharging currents through controlled skewing along with multi-node current starvation, the design achieves higher sensitivity of delay modulation compared to conventional inverter-based and current-starved VCOs. The proposed CSNS-VCO was fabricated in CMOS and allows a control voltage between 0.6 V and 7.5 V, thus giving the span of frequency tuning between 3 GHz and 13.7 GHz. This represents an 80
Quantum-dot Cellular Automata (QCA) is considered one of the most promising post-CMOS nanotechnologies to realize ultra-dense, low-power, and high-speed digital logic. The XOR gate is one of the basic logic modules in QCA-based circuits. It has a major effect on the performance of adders, subtractors, and hybrid combinational logic circuits. However, conventional XOR structures suffer from high cell overhead, long routing resources, and high propagation delay. To overcome these limitations, we propose a compact and efficient bi-layer XOR gate design. The proposed design is simple and highly efficient. This ultra-minimal three-input XOR gate comprises of nine cells in the first layer and one cell in the second layer, achieving a compact form factor while substantially reducing routing complexity. Using this three input XOR, we further design space optimized adder, subtractor and adder-subtractor organizations, offering improved layout compactness over the nearest prior-art designs. All circuits employ a bilayer configuration, avoiding signal crossing and preserving signal integrity. The functional verification (with QCADesigner 2.0.3 software) shows that all types of logical functions in their XOR, adder, subtractor, and hybrid versions are respected. The suggested layout achieves an 8.33
This paper presents the design and simulation of an analog signal separation technology. The circuit features a novel architecture with independently adjustable center frequencies. Simulation results demonstrate that such device has better effect than that of the similar signal separation system and is easy to be designed. This technology targets signal separation under conditions that the frequency range, waveform, amplitude and quantity of signals are specified. The main research contributions include the following: (1) Time–Frequency Analysis of Mixed Signals: A waveform identification scheme is developed by analyzing the characteristics of mixed signal C in the time–frequency domain. Precise algorithms and logical processing ensure the accuracy and reliability of the analysis results. (2) Signal Recovery and Synchronization: An effective signal separation and recovery mechanism are designed to ensure precise reconstruction of the separated signals. Simultaneously, a synchronized display function is implemented to match the original signal in frequency with zero drift, enabling intuitive signal comparison and analysis. (3) Flexible System lmplementation: A configurable system architecture is proposed to accommodate diverse waveforms and frequencies. Optimized algorithms and hardware resource allocation ensure efficient processing of various signals, delivering stable and reliable performance. The designed signal separation device fully meets the requirements for signal separation: input and output signals are separable, synchronized in frequency, and free from drift.
With the rapid advancement of Sixth Generation (6G) wireless communication systems, spectrum sensing is performed in Cognitive Radio Networks (CRN) to reliably identify spectrum holes in cognitive radios. In spectrum sensing, the idle frequency bands of the primary user are determined, and the secondary user is allowed the licensed spectrum without giving any interference to the primary user. Recently, various techniques have been used to utilize the underutilized spectrum bands fully for the prevention of essential radio demands from being denied. However, these techniques failed to increase the sensing performance by reducing power consumption. This paper presents a Quantum Reinforcement Learning_Magnificent Frigate Serval Optimization Algorithm (Quantum RL_MagFSOA) for spectrum sensing and management in 6G CRN. Here, the 6G cellular network with a dual-layer authentication procedure is considered. The Magnificent Frigate Serval Optimization Algorithm (MagFSOA) is designed for Master Blockchain Controller (MBC) selection. Then, sufficient spectrum access is obtained by spectrum sensing using Quantum Reinforcement Learning (Quantum RL) and predicting channel state information using Long Short-Term Memory-Multilayer Perceptron (LSTM-MLP). Following this, secure routing is performed using MagFSOA based on different parameters. Further, the Quantum RL_MagFSOA attained prediction accuracy, error rate, and power consumption of 95.469
To ensure convenient access to application data in Internet of Things (IoT) systems, seamless integration with wireless communication technologies is essential. This research proposes two broadband microstrip antennas—one for transmission and the other for reception—operating in the 2.4 GHz Industrial, Scientific, and Medical (ISM) band for IoT applications. The transmitting antenna, with dimensions of 42 × 42 × 1.6 mm³, features a U-shaped radiating structure fed by a microstrip transmission line. To reduce the antenna size and control the bandwidth (BW), a semicircular defective ground structure (DGS) was etched beneath the radiating patch. Furthermore, a T-shaped stub was incorporated at the centre of the U-shaped radiating element to achieve wideband operation. The receiving antenna measures 45 × 38 × 1.75 mm³ and consists of a circular ring with eight smaller circular rings distributed on its surface. In addition, a positive-sign-shaped structure with a central circular hole was introduced to further enhance the bandwidth. The antenna employs a circular ring-based fractal configuration, while the positive-sign structure, connected to the partial ground plane, reduces the capacitive reactance and further broadens the operating bandwidth. At 2.4 GHz, the transmitting and receiving antennas achieve radiation efficiencies of 90
In this work, a single-pass, hardware-compiled foreground offset calibration architecture for StrongARM dynamic comparators, targeting sub-10 mV input-referred offset at typical operating corners and bounded below 18 mV across the full process, voltage, and temperature (PVT) envelope, in 180 nm CMOS, is presented. The proposed method combines a custom single-layer perceptron, an on-chip time-to-digital converter (TDC), and a digitally controlled capacitor array for calibration. During the initial calibration phase, the comparator offset is measured as a timing deviation at the zero-crossing instant using the on-chip TDC; this timing value is then fed to the neural network, which predicts the optimal capacitor configuration in a single inference pass. The perceptron is synthesized to fixed integer weights with no hidden layer, eliminating iterative finite-state-machine (FSM) search, floating-point computation, and memory elements. By employing time-domain offset measurement and automatically generated capacitor settings, the proposed method eliminates time-consuming manual tuning and achieves precise foreground offset compensation without impacting normal conversion speed. Monte Carlo analysis at the TT corner (1.8 V, 27 ^∘ C, N=250 ) demonstrates that the 3 σ envelope of the mismatch-induced input-referred offset distribution is reduced from approximately 39 mV pre-calibration to 7 mV post-calibration, corresponding to an 82 μ _MC≈ 10 mV) is consistent with the nominal TT result of Table 10. Across full PVT sweep, post-calibration offset remains below 18 mV in worst-case conditions. Reported area numbers are pre-layout estimates from synthesized cell-level areas; the total estimated circuit area is 447 μ m ^2 , with neural inference logic occupying 35 μ m ^2 (8 μ W, making the architecture suitable for high-speed, high-resolution mixed-signal systems.
This Paper discusses the design circuit of Ka-band LNA CMOS Cascode Resistive Shunt Feedback (CCRSF) for the frequency range 26 GHz—28 GHz. Design steps, small-scale equivalent models and analytical expressions are derived. The design verification for operation in Ka band for the cloud RADAR receiver application is presented. For the proposed circuit, a simulation was carried out and compared with theoretical values. Narrowband LNAs offer low power consumption and low noise performance [14]. Wideband LNAs are suitable for larger bandwidths and signals with a large amount of noise. Wideband LNA designs are preferable for Ultra-Wideband (UWB), Cognitive Radio (CR), and Software-Defined Radio (SDR) communication system applications. A cascode configuration is employed with a resistive shunt-feedback topology, as this provides wide bandwidth, high gain, wideband input matching with minimum return loss, and low NF, thereby improving receiver sensitivity. By combining the cascode configuration with the resistive shunt feedback technique, a CCRSF LNA tunable to 28 GHz (mmW) was designed. Comparison results demonstrate that the proposed LNA employs a CCRSF design suitable for a cloud RADAR receiver in the millimeter Wave (mmW) range. The reported gain value is 33.2 dB, NF of 4 dB, power of 22.3 mW, and captured area of 0.399 mm2. The novelty lies in the design of LNA for Cloud CW RADAR operation at mmW frequency, with low noise figure, which is not reported earlier in other literature.
Digital Signal Processing (DSP) plays a crucial role in applications ranging from communications to multimedia. Finite Impulse Response (FIR) filters are widely used in audio, biomedical, and other signal processing domains, making their efficient implementation highly important. This work proposes the design of a low-power FIR filter on a Field Programmable Gae Array (FPGA) platform using the Carry Select Adder (CSLA) architecture combined with hybrid FinFET-GDI (Gate Diffusion Input) logic. The CSLA, with its parallelism and efficient carry handling, offers significant advantages for low-power DSP circuits. By optimizing the addition operation within the FIR filter, notable power savings are achieved. The integration of hybrid FinFET-GDI technology further enhances power-performance efficiency while reducing computation time. FPGA implementation on a Zynq 7000 board, supported by simulations in Tanner tool with 45nm technology and verification in Xilinx Vivado, confirms these improvements. Results show a 15
The capacity of processors to withstand the problems that arise from integrating CPU cores in a single IC is an ongoing requirement for digital signal processors (DSP). DSP is utilized for many processes such as convolution, transformation, correlation, and filtering. These processes entail multiplication, and successive additions impact the execution time and arrangement performance. Thus, multiplying and accumulating units (MAC) is essential in DSP. The MAC unit is focused on high-performance processes. Finally, DSP algorithms rely heavily on the MAC’s performance. The functionality of the proposed methods is tested using a Kintex, Artix, and Virtex Field Programmable Gate Array (FPGA) in Xilinx Vivado 2022.2 and ASIC 45 nm technology. Following a thorough investigation, we determined that the Urdhva-tiryagbhyam Vedic multiplication (UVM) technique with Pipelining(P) performed better than other multipliers. The present investigation describes the development of a high-speed MAC unit for arithmetic applications that use a high-speed pipelined Vedic multiplier (VM). The MAC unit’s VM and adder blocks are constructed using the Han Carlson adder (HCA). The proposed PUVMHCA provides considerable delay reductions of 43
Large automotive firms encounter major challenges when integrating renewable energy sources like fuel cells to power electric vehicles (EVs). Traditional boost and quadratic converters often encounter challenges in providing adequate voltage gain at practical duty cycles. DC–DC converters play a vital role in harmonizing the energy levels of fuel cells and electric vehicles, highlighting the importance of examining the specifications of both systems. This study introduces a Hybrid Quadratic Boost Converter (HQBC) topology with two variants (Type-I and Type-II) designed for fuel-cell powertrains. The converter models are analytically formulated and validated using MATLAB for a 27 V, 40 A, 1000 W fuel cell input. Results show that HQBC-Type II achieves a voltage gain of 18.8 at a duty cycle of 0.7, outperforming the conventional quadratic converter and HQBC-Type I. The switch voltage stress remains significantly lower than the output voltage (about 160–180 V), improving device reliability, while current stress stays within safe operating limits. The converter delivers 290 V, 3.2 A at around 980 W with a peak efficiency of 98.2
The adaptation of system-on-chip (SoC) in various communication systems, embedded systems, and automotive electronics fields has been explored, along with the advancement of integrated circuits (IC) fabrication. There are millions of SoC devices with underlying security threats named Hardware Trojan (HT), which impacts inadequate device authentication, leakage of secured information and modified functionality. This paper focuses on pre-silicon-based HT detection and machine learning (ML) techniques that automate feature data during training to identify HTs without the use of a golden chip. Existing pre-silicon learning approaches use a supervised model that is limited by the labelled feature set and requires a large amount of feature-related information during training. Therefore, an unsupervised model is proposed to tackle such a situation by training the unsupervised model with an unlabeled feature set to differentiate Trojan nets from normal nets. The proposed work uses the stacked sparse autoencoder (SSAE) to extract optimal features to train the ML model. The ensemble-based model is also attempted, which utilizes the balancing data from different classifiers to increase the detection accuracy. The unsupervised model obtains an average of 90.15
This study introduces a new, energy-efficient, fully analog integrated architecture of the Learning Vector Quantization algorithm. The design showcases its adeptness in effectively managing multiple input features, ensuring high precision, and minimizing power consumption. The main components of the algorithm are Gaussian function and argmax operator circuits. The operational concepts of the architecture are elaborated in detail and are applied to a power-efficient ( 1.28 μ W ) configuration with a low voltage (0.6V) setup. This implementation is tailored for two distinct classification tasks: digit recognition and bearing fault condition monitoring. utilizing a 90nm CMOS process, employing the Cadence IC Suite for both the schematic and physical design stages. Comparative analysis of post-layout simulation results with an equivalent software based classifier affirms the accuracy of the modeling and design methodologies employed.
