Distributed Arithmetic Based Hybrid Architecture for Multiple Transforms

Eight-point transforms play an important role in data compression, signal analysis and signal enhancement applications. Most widely used transforms of size -8 are Discrete Cosine Transform (DCT), Discrete Wavelet Transform (DWT), Discrete Sine Transform (DST), and Discrete Fourier Transform. There have been applications requiring multiple transforms for improving the performance. Unified/Hybrid architectures supporting multiple transforms is a possible solution for such demands as independent architecture for each transform requires more resources and computation power. In this work, a Distributed Arithmetic (DA) based multitransform architecture for supporting 1-D 8-point DCT, DFT, DST and DWT is proposed. A multiplier-less architecture leading to reduced hardware is implemented in 45 nm CMOS technology in Cadence RTL compiler as well as on FPGA using Xilinx ISE. Compared to the standalone transform architectures, there is 51.2% savings in number of adders, 44.34% saving in Look Up Table (LUT) utilization and 54.18% savings in register utilization in the proposed architecture.