Hardware Design and Implementation of High-Efficiency Cube-Root of Complex Numbers

This study presented an algorithm for fast hardware execution of complex cube root. In this algorithm, which is based on the Laurent series of ∛z function, first, the z-plane's numbers are mapped by using a rapid scaling and rotation operation to a pre-specified limited region, and then the sequences of the series are computed. The parameters of the algorithm are thoroughly analyzed and selected to achieve high precision. The algorithm has been implemented on a field programmable gate array-based platform using the Simulink HDL Coder tool and Xilinx ISE 14.7. In addition, the resource usage and speed parameters are carefully examined for the imple-mentation of each step of the algorithm. Hardware was implemented in two 56-bit and 32-bit versions (for comparison). The 32-bit version occupies 140 slice Regs, 421 slice LUTs, and 5 DSP48s. The hardware with the capability of computing complex cube roots has appropriate specifications comparable with those of previous implementations of real cube root calculation on FPGA.