High-Density Packaging Structure Optimization with Embedded Gate Driver for 3.3 Kv SiC MOSFETs

Medium voltage Silicon Carbide (SiC) power devices with superior performance are gradually becoming a commercial reality, especially the 3.3 kV rated SiC power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, an important brake for the adoption of WBG semiconductors in high power applications is the availability of well-optimized power module packaging as well as the learning curve in reliably driving them. To address these challenges, this paper presents a 3.3 kV Intelligent Power Module (IPM) packaging architecture featuring a compact, highly integrated, plug-and-play design that accelerates time-to-market and reduces engineering overhead. The proposed module integrates multiple 3.3 kV SiC MOSFETs and gate drivers within a single intelligent package, enabling not only improved system efficiency but also advanced control capabilities. A practical fabrication process is developed to realize this architecture, and 3.3 kV / 200 A full-SiC half-bridge IPM prototypes have been successfully assembled within a 104 × 100 × 24 mm footprint. Comprehensive static and dynamic characterizations validate the performance benefits of both the SiC devices and the proposed packaging solution. The demonstrated IPM represents a significant advancement in robust and intelligent power module design, with broad applicability across next-generation high-voltage power conversion systems.