GaN HEMTs, due to their high switching slew rates and zero reverse recovery current, have emerged as preferred devices for high-frequency and high-density power electronic systems. However, the high dv/dt and di/dt in a half-bridge can induce large crosstalk noise, resulting in false trigger or increased gate stress. This paper analyzes the generation mechanism of crosstalk noise in half-bridge circuits based on GaN HEMTs and performs mathematical modeling analysis of crosstalk voltage. Building upon the analytical results, a gate driver circuit based on an enhanced multi-level turn-off driver voltage profile for crosstalk noise suppression is proposed. By integrating an auxiliary branch that includes an N-MOSFET and an auxiliary capacitor, a low-impedance discharge path for positive crosstalk currents is generated and it can effectively mitigate positive voltage peak without external control signals. The design guidelines of the proposed gate driver circuit are presented. Both double pulse test and continuous operating test with a synchronous buck converter are conducted to demonstrate that the proposed circuit can significantly suppress crosstalk voltage peak without slowing down the switching slew rates of GaN HEMTs.

Two-phase direct immersion cooling offers significant thermal advantages for high-voltage power electronics, yet vapor formation fundamentally degrades dielectric performance. This work presents the first systematic comparative analysis of vapor-phase breakdown voltage (BDV) for four commercial dielectric fluids: SF10, HFE-347E, Novec 7200, and Novec 7500, using a custom vapor chamber enabling repeatable measurements across saturated liquid, vapor-liquid interface, and pure vapor conditions at 1.0mm electrode gaps. Vapor-phase operation consistently degraded dielectric strength by 35% to 47% across all fluids, with Novec 7500 demonstrating superior absolute performance (23.0 kV liquid, 14.8 kV vapor) and SF10 showing the most consistent cross-phase behavior. These findings establish that electrical insulation clearances in two-phase systems must be designed to vaporphase specifications.

Artificial intelligence (AI) is rapidly transforming power electronics, with AI-related publications in IEEE Power Electronics Society selected journals increasing more than fourfold from 2020 to 2025. However, the ethical dimensions of this transformation have received limited attention. This article underscores the urgent need for an ethical framework to guide responsible AI integration in power electronics, not only to prevent AI-related incidents but also to comply with legal and regulatory responsibilities. In this context, this article identifies four core pillars of AI ethics in power electronics: Security and Safety, Explainability and Transparency, Energy Sustainability, and Evolving Roles of Engineers. Each pillar is supported by practical and actionable insights to ensure that ethical principles are embedded in algorithm design, system deployment, and the preparation of an AI-ready engineering workforce. The authors advocate for power electronics engineers to lead the ethical discourse, given their deep technical understanding of both AI systems and power conversion technologies. The paper concludes by calling on the IEEE Power Electronics Society to spearhead the establishment of ethical standards, talent development initiatives, and best practices that ensure AI innovations are not only technically advanced but also oriented toward human and societal benefit.

Cryogenic power electronics attracts interests in diverse applications. When temperature decreases, Gallium Nitride (GaN) transistors show reduced static on-resistance, increased switching speed and enhanced breakdown voltage, all of which are favorable for cryogenic operation. The dynamic on-resistance dy $\boldsymbol{R}_{\boldsymbol{d s}(\boldsymbol{o} \boldsymbol{o})}$ of a GaN transistor can lead to excessive conduction loss, hence, must be quantified. Testing of $\mathbf{d y R}_{d s(o n)}$ requires an Onstate Voltage Measurement Circuit (OVMC), which has several types and none has been investigated for cryogenic operation. Therefore, cryogenic testing of dy $\boldsymbol{R}_{\boldsymbol{d s}(\boldsymbol{o} \boldsymbol{o})}$ only stresses the GaN transistor under test with cryogenic temperature and leaves the OVMC in room environment. It would be desirable to have a cryogenic-proof OVMC, which can be placed closely to the GaN transistor under test to improve signal integrity of instrumentation. This paper presents such a cryogenic OVMC, the functionality of which in $-\lt sup\gt1\lt/sup\gt|96^{\circ} \mathrm{C}$ environmental temperature is experimentally justified through its -3 dB bandwidth of1|5 MHz, 350 ns response time, $\lt3 \%$ error at frequencies up to1| MHz, and correct measurement of on-state voltage of a 650 V GaN transistor hard-switched at 250 kHz.

This chapter provides a quick tour of modern circuit simulation. It attempts to combine mathematical rigor with physical intuition, in order to provide a simple, clean exposition that links the various facets of the subject logically. The chapter shows how one can write circuit equations as nonlinear differential equations and comment on why it is a good idea to do so. It focuses on the important issue of noise analysis of circuits. The chapter outlines the fundamental concepts of basic stationary noise analysis and explain the kinds of circuits it applies to. It also focuses on special multitime partial differential equation (MPDE) forms for oscillators and also outlines how MPDEs can be used as a link to enable automatic macromodeling of time-varying systems. Advances in analog, radio frequency, digital, and mixed-signal design, combined with the effects of shrinking technologies, have spurred a renaissance in simulation.

This paper presents a full-bridge power module design for a dual-active bridge converter, featuring two parallel dies at each switching position. The proposed layout ensures identical parasitic parameters for all dies in both the DC commutation loop and the gate loop. Furthermore, symmetrical gate driver boards are integrated for the high-side and low-side switches, enhancing current sharing and reducing gate loop inductance. Embedded ceramic capacitors are included to lower the commutation inductance of the DC loop. For real-time thermal monitoring, a non-isolated NTC sensing circuit is introduced. The effectiveness of the design is verified through double-pulse testing (DPT) and converter-level experiments.

Medium voltage Silicon Carbide (SiC) power devices with superior performance are gradually becoming a commercial reality, especially the 3.3 kV rated SiC power Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs). However, an important brake for the adoption of WBG semiconductors in high power applications is the availability of well-optimized power module packaging as well as the learning curve in reliably driving them. To address these challenges, this paper presents a 3.3 kV Intelligent Power Module (IPM) packaging architecture featuring a compact, highly integrated, plug-and-play design that accelerates time-to-market and reduces engineering overhead. The proposed module integrates multiple 3.3 kV SiC MOSFETs and gate drivers within a single intelligent package, enabling not only improved system efficiency but also advanced control capabilities. A practical fabrication process is developed to realize this architecture, and 3.3 kV / 200 A full-SiC half-bridge IPM prototypes have been successfully assembled within a 104 × 100 × 24 mm footprint. Comprehensive static and dynamic characterizations validate the performance benefits of both the SiC devices and the proposed packaging solution. The demonstrated IPM represents a significant advancement in robust and intelligent power module design, with broad applicability across next-generation high-voltage power conversion systems.

Thermal management is crucial in power module design nowadays, significantly influencing the cost, performance, and reliability of the traction inverters. As we strive for greater power density and smaller form factors, innovative thermal solutions become imperative. In this study, we explored a two-phase cooling method for power electronics. The heatsink of a hybrid single- and two-phase cooler is integrated into a power module. We utilize surface enhancement features at the substrate-embedded evaporator to enable capillary-driven flow for passive coolant circulation and optimized phase separation. Additionally, a local reservoir is included in the cooler package that serves as a buffer to optimize the liquid supply to the evaporator. The two-phase cooling in our study leads to a high heat flux removal rate of 370 W/cm2 at a low superheat of 10 degrees C, and the coolant flowrate is less than 1 g/min, nearly 50 times lower than the pumped flow-based two-phase microcoolers. The feasibility of the completely passive operation is also studied. The proposed two-phase embedded cooler provides a promising solution for effective cooling and heat spreading of the next-generation power modules.

Recyclability is being pursued in power electronics. Power semiconductor devices and modules are some of the core components, featuring high material and energy costs in fabrication, but with limited service lifetime. This study explores a packaging structure that might improve their recyclability in the future. The study focuses on the cooling and electric insulation aspects of the substrate-less design. A customized three-sectional heat pipe is used to replace the ceramic-based direct bonded copper (DBC) or active metal brazed (AMB), which are difficult to recycle. It is assumed that the commonly used thermoset plastic casing and silicone gel can be replaced by recyclable polyetherimide (PEI) encapsulation. A design procedure is proposed to match the specifications of the heat pipe with the thermal dissipation and electric insulation requirements of the power device. The thermal resistance of junction heatsink is shown to be much lower than that of a typical substrate. The electric insulation strength is compared for different working fluids to identify a satisfactory solution.

Synchronous buck converters (SBCs) on EV auxiliary rails face coupled trade-offs among conversion efficiency, LC-filter volume, and output ripple. We present a surrogate-assisted multi-objective workflow that couples a hybrid GA–PSO search with a batch-normalized neural surrogate trained on 5,992 PLECS simulations using physics-linked features (duty, inductor ripple, flux-density swing, LC cutoff). The surrogate attains on all objectives and per-evaluation speedup; periodic high-fidelity re-checks (of evaluations) anchor accuracy. Under a 12,800-evaluation budget, the hybrid method outperforms NSGA-II and MOEA/D (hypervolume +12.3%, IGD – 43.8%) and cuts end-to-end optimization time from 37 h to 45 min (49×). The final 51-design Pareto set spans, cm3, and ripple at 48→12 V, 100 W, 20 kHz, with all nominal designs meeting a limit. Sensitivity and tolerance studies show compact points are fragile (e.g., 56% compliance under ±20%), whereas knee designs maintain robustness. The workflow generalizes to other topologies and supports distributed evaluation for scalable power-electronics design automation.

As the negative impact of climate change escalates, the global necessity to transition to sustainable energy sources becomes increasingly evident. Renewable energies have emerged as a viable solution for users, with Photovoltaic (PV) technology being a favored choice for small installations due to its high reliability, competitive market and increasing efficiency. Accurate mapping of PV installations is crucial in improving grid management, facilitating the integration of renewable energy, encouraging active participation from prosumers, and optimizing the economic performance of decentralized energy markets. To meet this need, S3Former is introduced, which is designed to segment solar panels from aerial imagery and provide size and location information critical for analyzing the impact of such installations on the grid. Although computer vision has become a preferred choice for such implementations, solar panel identification is challenging due to factors such as time-varying weather conditions, different roof characteristics, Ground Sampling Distance (GSD) variations and lack of appropriate initialization weights for optimized training. To tackle these complexities, S3Former features a Masked Attention Mask Transformer incorporating a self-supervised learning pretrained backbone. Specifically, the model leverages low-level and high-level features extracted from the backbone and incorporates an instance query mechanism incorporated on the Transformer architecture to enhance the localization of solar PV installations. Moreover, a self-supervised learning (SSL) phase (pretext task) is introduced to fine-tune the initialization weights on the backbone of S3Former, leading to a noticeable improvement on the results. To rigorously evaluate the performance of S3Former, diverse datasets are utilized, including GGE (France), IGN (France), and USGS (California, USA), across different GSDs. Our extensive experiments consistently demonstrate that the proposed model either matches or surpasses state-of-the-art models (SOTA) and validate the benefit of using the SSL method to improve the segmentation architecture. Source code is available upon acceptance.

Electronics Design Automation (EDA) has shown significant importance in the power electronics industry. As power electronic circuits become more complex, the traditional trial-and-error approach in physical design becomes less effective and time-consuming. Novel packaging technologies and intelligent physical design automation solutions are crucial to overcome these challenges and produce reliable solutions. PowerSynth 2 is an EDA tool for generating and optimizing power module layouts. To extend the layout synthesis capability beyond power modules, the layout engine needs to consider various custom components such as capacitors, inductors, and gate drivers. This research presents a novel framework for the layout synthesis process in PowerSynth 2 to allow importing user-defined components. The proposed algorithm can effectively generate a Power Electronics layout by introducing a hierarchical framework for custom components and pin pads. It will extend the physical design process to broader design types, such as converters and server boards. Examples of converter designs are tested, demonstrating the efficiency and scalability of the proposed design tools.

Gallium oxide (Ga2O3) has recently become a highly intriguing semiconductor, particularly in the field of power electronics. Ultra-wide bandgap (similar to 5 eV) and higher dielectric constant (similar to 10.5-12.5) are the two properties far better than silicon carbide (SiC) and gallium nitride (GaN). beta-Ga2O3 is the most stable phase among the five polymorphs (alpha, beta, gamma, delta, and epsilon). Moreover, a key advantage of beta-Ga2O3 over SiC and GaN is its ability to produce high-quality native crystals at a lower cost. Devices based on beta-Ga2O3, such as Schottky barrier diodes and depletion-mode lateral MOSFETs, have demonstrated stable I-V characteristics at voltages exceeding 1 kV. However, limited research has been conducted on the capacitance-voltage (C-V) analysis of beta-Ga2O3 devices. This paper presents a TCAD simulation of a beta-Ga2O3 depletion-mode lateral MOSFET (DMOSFET), which exhibits stable characteristics up to 370V. The reverse transfer capacitance (Crss), output capacitance (Coss), and input capacitance (Ciss) of the device were analyzed using Silvaco. The lower capacitances are expected because of the higher dielectric constant of beta-Ga2O3. Additionally, the electron concentration distribution was studied to illustrate the expansion of the depletion region with increasing drain voltage. These findings provide valuable insights for future modeling and optimization of beta-Ga2O3 depletion-mode lateral MOSFETs.

The adoption of double-sided cooled (DSC) module packaging remains limited by fabrication complexity, despite its promise for high-power silicon carbide (SiC) applications. This work presents fabrication-process advancements for a 1.2 kV half-bridge DSC SiC power module with integrated gate driver and decoupling capacitors. The objective is to establish manufacturable strategies that enhance insulation reliability and functional integration. Key improvements include optimized topside chip pad re-metallization for robust double-sided die attachment, a revised assembly sequence enabling modular gate driver integration with reworkability, and enhanced alignment control to ensure structural consistency. Using the optimized process, 1.2 kV/164 A full-SiC MOSFET half-bridge prototypes were assembled. Static and dynamic evaluations confirm that the refined process effectively supports reliable DSC module realization.

In order to reduce the size, weight, and cost of power electronic systems, a high-temperature silicon carbide (SiC)-based half-bridge power module is proposed in this article. Two gate drivers, which were fabricated on low-temperature co-fired ceramic (LTCC) substrates, are integrated into the power module to reduce the gate loop inductance and size of the power module. The design and fabrication process of the LTCC-based gate driver is presented. In addition, the layout design, simulations, and fabrication materials of the power module are also discussed. High-temperature components and materials were implemented to fabricate the power module, which allows it to operate up to 200 C-degrees. Double pulse tests (DPTs) were carried out from 25 C-degrees to 200 C-degrees to investigate its switching performance. The turn-on and turn-off dv/dt of the power module is from 10 to 15 V/ns, and little degradation was observed at elevated temperatures. While the power module achieves functional integration and promising thermal performance, the operating temperature is limited by the gate driver integrated circuit (IC). A high-temperature gate driver IC will be designed and integrated into the power module in future work to improve thermal reliability. This work provides a critical foundation for the development of high-temperature and high density power modules.

As climate change accelerates, the global transition to clean and sustainable energy is increasingly urgent. Photovoltaic (PV) energy is a preferred choice due to its reliability and ease of installation. However, effective management of PV systems requires (i) precise and real-time localization of solar PV installations for global profiling and (ii) accurate assessments of real-time output voltage and system performance. To address these challenges, we propose a dual-approach solution for comprehensive solar panel analysis leveraging both satellite and UAV imagery. Our method first segments and maps solar panels from satellite images, providing critical insights into their geographic distribution and size. Simultaneously, it analyzes unmanned aerial vehicle (UAV) imagery to prevent degradation caused by obstructions on the solar panel surface, such as leaves, branches, dust, and bird droppings, while also assessing the overall condition of solar PV systems. To further advance the field, we introduce the De-Solar dataset, a novel, high-quality collection of labeled solar panel images focused on diverse obstructions types, designed to train computer vision models. Solar panel identification presents unique challenges due to variations in weather conditions, roof textures, obstruction types, and Ground Sampling Distance (GSD). To address these complexities, we propose SolarFormer++, a state-of-the-art model featuring a multi-scale Transformer encoder and a masked-attention Transformer decoder. The proposed model leverages low-level image features and employs an instance query mechanism to enhance localization of solar PV installations and precise obstruction detection. For global-scale solar PV profiling, we evaluate SolarFormer++ across diverse public datasets, including GGE (France), IGN (France), and USGS (California, USA), spanning varying GSDs for global-scale analysis. To detect obstructions in order to prevent degradation and assess performance, we benchmark the proposed SolarFormer++ on our newly introduced De-Solar dataset. Experimental results consistently demonstrate that SolarFormer++ outperforms existing methods.

This article proposes the generalized design guideline for micrometer silicon carbide (SiC) complementary metal-oxide-semiconductor (CMOS) devices for integrated circuit (IC) applications. The design window of 1- $\mu $ m SiC CMOS devices, which considers device operation voltage, on-state current, short channel effect (SCE), and subthreshold swing (SS), is proposed to show the design margins of the gate oxide thickness and channel doping concentration. The performance of CMOS devices in 1- $\mu $ m SiC CMOS processes is used to demonstrate the effectiveness of the proposed design window. SiC-based buffer chain circuits are tested to demonstrate circuit operating speed and power consumption. The devices and circuits are fully characterized from 25 degrees C to 300 degrees C. It has been demonstrated that further design improvements for SiC CMOS devices are needed before large-scale implementation due to their strong SCE, high SS, and lowon-state current. On the other hand, SiC ICs show less degradation with increasing temperatures compared to Si ICs, making them promising for high-temperature applications.

The packaging used for power modules can be the dominant thermal resistance, greater than the convective thermal resistance. The use of advanced heat spreaders within the power module can enable improved heat dissipation, resulting in lower package conduction resistance. Advanced heat spreading is even more beneficial for silicon carbide (SiC) devices given their smaller size and higher heat fluxes. This paper evaluated the use of vapor chambers, graphite-based, and copper (Cu)-diamond heat spreader technologies as possible thermal management solutions for SiC double-side-cooled power modules. Experimental measurements with a vapor chamber were conducted and were consistent with what is reported in the literature, demonstrating that current vapor chamber technology is not suited for automotive power electronics applications. Thermal modeling of advanced module concepts that integrate heat spreaders within the power module predict enhancements as compared with the baseline module without a heat spreader. Cudiamond heat spreaders are predicted to be more effective at reducing the module’s thermal resistance as compared with graphite-based heat spreaders. Finally, transient thermal models were developed and used to predict the temperature response for the advanced modules for a representative drive cycle.

Gallium Nitride power devices, with an energy bandgap roughly three times larger than that of silicon, provide lower specific conduction resistance and faster switching speeds. These characteristics enable the design of more efficient and compact power converters. However, challenges such as high voltage overshoot during rapid switching transients continue to limit the full potential of GaN technology. This study presents an innovative alternative to the conventional wire-bonded GaN power module through the development of a flip-chip design employing solder ball bonding. A detailed finite element analysis (FEA) model is constructed to evaluate the junction temperature and parasitic inductance of power modules. Furthermore, the bonding strength is examined to ensure the mechanical integrity of the design. The proposed flip-chip design is experimentally validated by static characterization and double pulse test. The design reduces parasitics and enables compact, efficient GaN power electronics for high-frequency use.