High-performance Schmitt Trigger Buffer with DTMOS Integration

This article presents an optimised design of a Schmitt trigger buffer using DTMOS technology, aimed at achieving higher speed and lower noise margin. Two modified circuits are proposed: a noise-immune DTMOS Schmitt trigger that effectively suppresses noise and a high-speed DTMOS Schmitt trigger that operates with reduced power consumption. The key objectives of this work are to reduce transistor count, minimise power usage, decrease noise and delay, and lower switching current. DTMOS devices, capable of operating at low voltages and high speed, are particularly suitable for energy-efficient applications. In contrast, CMOS-based designs lead to increased power, delay, and noise. The noise-immune DTMOS circuit, which includes feedback, achieves a hysteresis width of 159 mV at 0.3 V, which increases to 254 mV at 0.5 V - enhancing its noise-filtering capability. The high-speed DTMOS circuit exhibits a narrow hysteresis width of 6 mV, switching ON at 1.2 V and OFF at 1 V, indicating fast operation. Both circuits demonstrate efficient low-voltage performance, highlighting DTMOS as a superior alternative to CMOS for low-power, high-speed digital applications. The design is implemented in 90 nm technology using the cadence virtuoso tool and operates at a low supply voltage of 0.3 V.