High-performance Two's Complement Divider

This paper presents a novel area-efficient two's complement high radix divider without affecting the high speed of the radix-2k structure. In the proposed approach, only the odd values (rather than all the 2k values) of the quotient digit set are used to generate the multiples of divisor. Moreover, the set of (N+k+1)-bit additions are replaced with a set of few most significant bits (k+2 bits) additions followed by two (N+3)-bit additions only. The new radix-2k structure has been evaluated for different values of k. It is shown that the silicon area required by the new design could be as low as 15% of that of the conventional two's complement radix-2k architecture for radix-64 (20% for radix-32) while the speed is nearly the same. Despite that the proposed algorithm is originally developed in order to improve the performance of the two's complement approach, it has also been compared with the redundant SRT algorithm. The area–time ratios of the new radix-16 and radix-32 dividers to that of the SRT divider are equal to 85% and 77%, respectively.