This paper presents a novel area-efficient two's complement high radix divider without affecting the high speed of the radix-2k structure. In the proposed approach, only the odd values (rather than all the 2k values) of the quotient digit set are used to generate the multiples of divisor. Moreover, the set of (N+k+1)-bit additions are replaced with a set of few most significant bits (k+2 bits) additions followed by two (N+3)-bit additions only. The new radix-2k structure has been evaluated for different values of k. It is shown that the silicon area required by the new design could be as low as 15% of that of the conventional two's complement radix-2k architecture for radix-64 (20% for radix-32) while the speed is nearly the same. Despite that the proposed algorithm is originally developed in order to improve the performance of the two's complement approach, it has also been compared with the redundant SRT algorithm. The area–time ratios of the new radix-16 and radix-32 dividers to that of the SRT divider are equal to 85% and 77%, respectively.

This paper presents an area-efficient twos complement high radix division algorithm and its architecture. The advantage of using high radix division is to generate more quotient bits per iteration while binary division results in one bit per iteration. In the conventional restoring radix-2^k division, the selection of the quotient digit requires the use of all the multiples of the divisor. As a result, the area increases exponentially (area of radix 2^k divider is about 2^k times the area of binary divider) while the speed increases linearly (speed of radix 2^k divider is approximately k times that of binary divider). In this paper, a new algorithm that makes use only of the even multiples of the divisor is proposed. The area is nearly halved since the number of multiples is reduced from 2^k to 2^k^-^1. We use the even multiples rather than the odd ones because the even multiples are easier to generate and some of them are produced by simply shifting the divisor. For example, the even multiples 2D and 4D are generated by shifting D one and two bits to the left, respectively, while the odd multiples 3D and 5D require an addition of D to 2D and D to 4D, respectively.

In this paper, a new two's complement radix-2n area-efficient digit serial divider is presented. The proposed digit serial divider is designed by cascading N (wordlength) digital controlled add/subtract DCAS cells where each cell is used to generate one of the N quotient bits. Two types of the DCAS cells namely a carry select controlled add/subtract CSCAS cell and a carry generate controlled add/subtract CGCAS are proposed. The new DCAS cells can be fully pipelined to the bit level using only one set of cuts. The proposed pipelined divider could achieve the same throughput rate as the existing ones by using nearly half the number of pipelining levels. As a result, it requires less silicon area and it has less initial delay. The new digit serial divider is based on radix-2n arithmetic and therefore, it is simple and general for any digit size, n. Any adder can be used to perform the n-bit addition of the DCAS cells.

This paper presents an area-efficient 2's complement high radix division algorithm. Two techniques are used in the proposed radix-2k division algorithm, which result in a significant reduction in the required silicon area. First, the number of full wordlength additions is halved from 2k to 2k-1. Second, the full wordlength additions are replaced with a set of (k+2)-bit additions only

This paper presents an area-efficient 2's complement high radix division algorithm. Two techniques are used in the proposed radix-2/sup k/ division algorithm, which result in a significant reduction in the required silicon area. First, the number of full wordlength additions is halved from 2/sup k/ to 2/sup k-1/. Second, the full wordlength additions are replaced with a set of (k+2)-bit additions only.

In the above paper, [see ibid., vol. 47, p. 369-70, 2000] the authors have modified the nonrestoring square root algorithm (Q=/spl radic/A) and its architecture [see ibid., vol. 38, p.358-75, 1991] to give correct results. They claimed that the partial remainder (PR) should be kept as is rather than eliminating its MSB at each step of the algorithm. Since two bits of A are appended to PR at each step of the algorithm, length of kth PR will be 2k rather than k+1 as in the algorithm of [1]. They also suggested that k of 0's to be appended to the left of the MSB of the radicand to keep its length as that of PR. As a result, k-1 CAS cells are added to the kth row of the architecture. In this comment, it will be shown that most of the additional CAS cells are redundant where only one added CAS cell per each row is enough to compute the correct square root.

The conventional two's complement radix-2k square root algorithm requires a set of 2k full precision comparisons to generate all the 2k possible values of the partial remainder. The correct remainder is the minimum positive one of the 2k possible values. Since the number of adders of the 2k full wordlength comparisons increases exponentially with k, a huge area is required to implement this algorithm, especially for high values of k. The paper presents a new two's complement high radix square root algorithm. For the first time, the 2k full wordlength additions are replaced with 2k one-digit (i.e. k-bit) additions only. It has been shown that the one-digit additions are enough to reduce the number of possible values of the partial remainder from 2k to two values only. Then, only two full wordlength additions are required to select the minimum positive value of these two values as the correct remainder. As a result, the silicon area is reduced significantly while the speed is nearly the same. Moreover, the new algorithm can be made faster by using one of the known fast adders because it requires only two (rather than 2k) full wordlength additions. From the evaluation of the proposed structure, it has been shown that the required area is reduced by 65% for radices of 32 and 64

The conventional two's complement digit serial square root structure processes an n-bit digit every clock cycle. Therefore, it generates one bit of the N-bit square root every m cycles, where m = N/n. Instead of generating K bits every mK cycles, these bits can be generated in m + K - 1 cycles only by overlapping K steps of the conventional digit serial algorithm. The new two's complement structure is a tree representation of the conventional one and therefore, it can be considered as a high radix approach of the digit serial structure. It will be shown that the proposed architecture is faster and might be cheaper than the conventional digit serial one. Moreover, it is the first digit serial square root structure which is cheaper and faster than the two's complement binary bit parallel one.

A novel digit serial combined arithmetic unit for multiplication, division and square root which can be pipelined to the bit level is presented for the first time, The proposed module is based on radix-2(n) arithmetic. As a result, it is general for any digit size, n, and can be derived in a straightforward manner without the need to bit parallel or bit serial designs as an initial starting point. Moreover, any adder can be used in the controlled add/shift/subtract basic cell of the generalised digit serial unit. Two digital basic cells are proposed; the first cell is based on the conventional carry feedback adder and hence, the digit serial structure can be pipelined to the digit level only. The second digital cell is based on the carry fed forward adder. The feed forward of the carry out bit allows subdigit pipelining to increase the computation speed. This will give designers greater flexibility in finding the best trade-off between hardware cost and throughput rate. An evaluation of the proposed structure is also presented. It is shown that the bit level pipelined digit serial architecture can achieve better performance than the conventional carry feedback digit serial design and the bit parallel one. (C) 1999 Elsevier Science B.V. All rights reserved.

It is well known that the existing two's complement radix-2k division methods require a set of full wordlength comparisons of the multiples of the divisor against the shifted remainder. For fast division, these comparisons should be implemented in parallel. Therefore, a huge area is required to implement such high radix division. The paper presents a novel two's complement radix-2k division algorithm. For the first time, the set of full precision additions are replaced with a set of (k+2)-bit additions. Then, only two full wordlength additions are required to select the k-bit quotient digit out of two values selected by the (k+2)-bit comparisons. As a result, the required area is reduced by 77% with the speed of the two algorithms are nearly the same. Moreover, the speed of the new algorithm can be made faster by using one of the known fast adders because only two full precision additions (rather than the set of the full precision additions) per radix-2k quotient digit is required

The existing two's complement high radix division algorithms require a full wordlength addition per each possible value of the remainder. Therefore, a huge area is required to implement these algorithms. This paper presents a novel two's comple- ment radix-2' structure which replaces the! full wordlength addition with a (k+2)-bit ad- dition. Therefore, the required area is re- duced significantly without any reduction in speed.

The existing two's complement high radix division algorithms require a full wordlength addition per each possible value of the remainder. Therefore, a huge area is required to implement these algorithms. This paper presents a novel two's complement radix-2k structure which replaces the full wordlength addition with a (k+2)-bit addition. Therefore, the required area is reduced significantly without any reduction in speed

This paper presents a new high radix square rooting algorithm where a number of square root bits (one digit) are generated in one step. Therefore, the proposed algorithm offers a higher speed than that of the conventional bit parallel binary one. This algorithm can be considered as a generalisation of the conventional bit parallel binary algorithm, and therefore it can be implemented using the existing simple binary elements. The proposed algorithm makes use only of the odd values of the square root to generate the possible values of the radicand and therefore, it requires less area than the conventional restoring high radix algorithm which uses all the values of the square root. This algorithm is general for any radix. Any adder can be used in the basic cell, it can be a carry ripple adder or a carry lookahead adder. As an example of a radix-2(k) square root architecture, a 9-bit radix-2(3) architecture is presented in this paper.

A new area-time efficient digit serial division algorithm and its architecture are presented. In existing digit serial algorithms based on 2's complement number representation, rn cycles are required to generate each quotient bit (m is the number of radix-2(n) digits of the word. N). In the new algorithm, K quotient bits are generated in m+K-1 cycles instead of mK cycles. Performance comparisons have shown that the new algorithm is up to K times faster and moreover for small values of K it requires a smaller area than existing digit serial algorithms that are based on 2's complement number representation. More significantly, by comparing the new structure with the conventional binary bit parallel one, it has been shown that the new structure is faster and requires a smaller area.

A new radix digit serial division algorithm is presented. The speed of the proposed algorithm is nearly twice that of an existing design. Moreover, the new algorithm requires less area for a digit size of up to 8 bits (for a 32 bit quotient).

This paper presents a new radix-2(k) non-restoring area-efficient fast divider architecture where k quotient bits (one digit) are calculated in one step. Unlike the existing non-redundant high radix architecture, the proposed architecture makes use only of the odd multiple values of the divisor. Therefore, it requires nearly half the area of the existing one. The input operands are in the two's complement form, whereas the output quotient is in the r's complement form. This architecture is general for any value of k and can deal with positive and negative operands. Any adder can be used in the basic cell. This can be a ripple carry adder or a carry lookahead adder.

A new digit-serial square-root architecture based on radix-2'' arithmetic is presented. First, the conventional binary square-root algorithm is modified to a digit-serial algorithm which is used to design the proposed architecture. This architecture consists of a number of n-bit controlled add/subtract (CAS) cells. We present two CAS cell architectures. The first is based on the conventional carry feed-back digit serial adder. The second is based on the carry feed-forward adder structure which results in the first reported square-root architecture that can be pipelined down to the bit-level. Furthermore, there is no specification of the type of adder used in the CAS cell. It can be a carry look-ahead or a carry propagate adder. The proposed architecture is general for any digit size and any wordlength.

The paper presents a new digit-serial architecture for division and square-root which can be pipelined to the bit level to achieve high throughput. The architecture is different from the existing divider/square-root architectures in that it is based on the radix-2n algorithm. As a result, any type of adder can be used in the proposed digit-serial controlled add/subtract basic cell. The authors present two basic digit-serial controlled add/subtract cells. The first is based on the conventional carry feedback digit-serial adder. The second is based on the carry feed-forward adder, which results in the first reported digit-serial divider/square-root architecture that can be pipelined down to the bit-level. An evaluation of the proposed architecture for different values of the digit size is also presented

A digit-serial squaring architecture based on radix-2n arithmetic is presented to carry out squaring digit serially. In this paper, the conventional binary squaring algorithm is modified and a radix-2n squaring algorithm which is used to design the proposed architectures is presented. The resulting basic cell is the Digital Controlled Add/shiFt (DCAF) cell. The advantage of using radix-2n arithmetic is that it specifies the functionality of the DCAF cell only and, hence, there is no restriction on the type of adder to be used. It can be a ripple carry adder, a carry lookahead adder, a pipelined adder, or a carry-save adder. The merit of the new structure is that it provides system designers with a great deal of flexibility to find the best trade-off between cost and throughput by varying the radix, the type of adder to be used and/or the number of pipelined stages.