High-speed Programming with Threshold Division for RRAM-based Neural Network Accelerators

RRAM-based neural network accelerators offer significant improvements in energy efficiency and throughput for machine learning and artificial intelligence. However, it is challenging to transfer trained neural network weights to RRAM arrays precisely due to non-ideal characteristics such as read noise and write variability. A write-verify strategy is commonly employed to adjust the RRAM cells within acceptable error margins. However, this process is time-consuming and resource-intensive. In this work, a high-speed programming strategy based on threshold division is proposed, inspired by magnitude-based network pruning. The relationship between threshold conductance and programming error is systematically investigated by allowing a larger programming error for cells below the threshold. Results of experiments on MLP and LeNet-5 networks demonstrate that the programming speed is enhanced by 3.41 times and 2.39 times, respectively. This strategy provides a novel method for fast transfer of weights in large-scale RRAM-based neural network accelerators.