Scienti c computing and image processing applications access large amounts of data in regular patterns In order to relieve the memory bottle neck caching tries to keep recently referenced data available in fast storage This is increasingly important as the gap between processor and memory hierarchy speed has widened in recent years There are two main di culties that cannot be dealt with by hardware alone Firstly a cache line usually holds several values often only one of them is actually used Secondly con icting accesses to one cache line cause data to be evicted which is still required In the extreme case data is replaced on every access a situation we denote as cache thrashing To overcome these problems the temporal spatial structure of accesses has to be changed Compile time cache optimizations exploit regular access patterns Loop transformations as e g tiling are well established For caches with limited associativity it is often crucial to additionally adjust the placement of data in memory We show that compiler techniques for register allocation namely graph coloring support a systematic data placement For innermost loops con icts and temporal reuse can be modeled to gether in a cyclic interval graph If reuse stretches over several loop itera tions live ranges may overlap themselves prohibiting usual cyclic coloring By applying the meeting graph method the compiler can determine an un rolling factor and determine the maximal number of colors i e of cache lines required Values of the same color are mapped to memory together Since these values may stem from di erent data structures our technique o ers a nat ural way of dealing with con icts between di erent arrays We implement this scheme through modifying the standard memory mapping At run time the new compile time mapping function is used as index function The tradeo between the additional cost for more complex indexing and reduced miss penalty is re ected by a cost function For typical example codes from the above areas reuse and con ict be havior are considerably improved yielding moderate run time reductions In addition on a more coarse level paging activity is often signi cantly postponed
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