High-level synthesis systems overcome the high design effort required to program an FPGA by translating an algorithm at the behavioral level into a synthesizable hardware description. At this higher level, loop transformations are used to improve the characteristics of the program. These transformations have a great impact on the resulting hardware, only known after the timeconsuming synthesis steps. This hinders a fast design space exploration. In this paper, we tackle this issue by estimating the performance of the hardware loop controller, an often overlooked component in other approaches. We present an equation based model to estimate the area of the loop controller during high-level synthesis. The presented approach is accurate enough to be useful during design space exploration. Due to its simplicity, the overhead of the estimations is minimal. The proposed methodology can easily be adapted to new FPGA design flows and architectures.
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