Multi-die FPGAs enable device scaling beyond reticle limits but introduce severe interconnect overhead across die boundaries. Inter-die connections, commonly referred to as super-long lines (SLLs), incur high delay and consume scarce interposer interconnect resources, often dominating critical paths and complicating physical design. To address this, this work proposes an interconnect-aware logic resynthesis method that restructures the LUT-level netlist to reduce the number of SLLs. The resynthesis engine uses die partitioning information to apply logic resubstitutions, which simplifies local circuit structures and eliminates SLLs. By reducing the number of SLLs early in the design flow, prior to physical implementation, the proposed method shortens critical paths, alleviates pressure on scarce interposer interconnect resources, and improves overall physical design flexibility. We further build a tool flow for multi-die FPGAs by integrating the proposed resynthesis method with packing and placement. Experimental results on the EPFL benchmarks show that, compared with a state-of-the-art framework, the proposed method reduces the number of SLLs by up to 24.8% for a 2-die FPGA and up to 27.38% for a 3-die FPGA. On MCNC benchmarks, our tool flow achieves an average SLL reduction of 1.65% while preserving placement quality. On Koios benchmarks, where fewer removable SLLs exist, several designs still exhibit considerable inter-die edge reductions. Overall, the results confirm that reducing inter-die connections at the logic level is an effective approach for multi-die FPGAs.

In this paper, we study a calibrated 15 nm gatelength CFET model, developed using TCAD simulations and experimental data from TSMC. CFET architectures enable better electrostatic control and footprint reduction for next-generation logic gates beyond the 3 nm node. The effect of fin thickness and extension engineering in the sources/drain regions on device performance w/o inclusion of self-heating effects (SHE) is investigated. SHE is one of the main challenges of reliability for the current technology nodes. Systematic analysis shows that the increase of fin thickness can improve heat dissipation and reduce delay but degrade on-state current. Simulations of AC CMOS inverters show that the reduction of the S/D extensions can lead to an increase in the on-state current and to faster switching. However, this may cause an increase in the dynamic power consumption, heat dissipation, and the appearance of shortchannel effects and leakage currents. Also, the doping density of the S/D extension is changed in order to simulate different contact resistances, and a strong trade-off between switching speed and power consumption is demonstrated. These results offer useful design guidelines for CFET technology development.

As semiconductor scaling approaches the sub-3 nm regime, conventional FinFET architectures face increasing challenges in controlling short-channel effects (SCEs) while maintaining power-performance-area (PPA) efficiency. Complementary FET (CFET) architectures, which vertically integrate nFET and pFET devices, offer improved electrostatic control and a reduced footprint, making them strong candidates for next-generation logic technologies. In this study, three-dimensional FinFET and CFET structures with a 15 nm gate length are modeled and calibrated using experimental data from IBM and TSMC via TCAD tools. After validation, the models are employed to systematically examine the impact of fin width, fin height, gate length, source/drain extension length, and gate stack engineering on both DC and RF performance. Key metrics including threshold voltage (V-th), subthreshold slope (SS), drain-induced barrier lowering (DIBL), on/off current ratio (I-on/I-off), transconductance (g(m)), gate capacitance (C-gg), intrinsic delay (tau), cut-off frequency (f(T)), and power are analyzed in detail. We investigated source/drain extension doping corresponding to contact resistances from 5 x 10(-10) to 5 x 10(-9) Omega cm(2). Lower contact resistance improves drive current and operating speed but increases dynamic power by similar to 26.5 %, illustrating the inherent speed-power trade-off crucial for CFET layer design across technology nodes. Overall, our geometric and material optimizations significantly enhance CFET performance, providing practical design guidelines for low-power, high-performance applications in advanced technology nodes.

The physical design phase of FPGA programming includes the placement step, where logic blocks of the netlist are mapped to hardware primitives. This work explores an hierarchical strategy for initial placement that reduces complexity of the placement problem by first grouping related blocks into clusters. Such reduced netlist could further be used during placement optimization. Here, a placement is made in two stages: an intercluster placement to determine coarse locations, followed by intra-cluster refinement. Experimental results demonstrate that the approach achieves comparable timing and wirelength quality to existing methods, although runtime performance remains an area for further tweaks.

In the realm of programmable photonic integrated circuits (PICs), precise wire length control is crucial for the performance of on-chip programmable components such as optical ring resonators, Mach-Zehnder interferometers, and optical true time-delay lines. Unlike conventional routing algorithms that prioritize shortest-path solutions, these photonic components require exact-length routing to maintain the desired optical properties. To address these challenges, this paper presents different length-matching routing strategies to find exact-length paths while balancing search space and runtime efficiently. We propose a novel admissible heuristic estimator and a pruning method, designed to enhance the accuracy and efficiency of the search process. The algorithms are derived from the Best-First search with modified evaluation functions. For two-pin length-matching routing, we formally prove that the proposed algorithms are complete under monotonic heuristics. For multi-pin length-matching challenges, we introduce a pin-ordering mechanism based on detour margins to reduce the likelihood of prematurely blocking feasible routes. Through evaluations on various length-matching benchmarks, we analyze runtime and heuristic performance, demonstrating the effectiveness of the proposed approaches across different layout scenarios.

Packing is a crucial step of FPGA design, directly impacting interconnect complexity, routing congestion, and overall performance. This paper presents a post-packing interconnect-aware analysis, illustrating how dense (sparse) packing changes the interconnection structure. We introduce a new metric, RDensity, to define post-packing density and investigate its influence on routability. Through a comparative study of two packing tools, we demonstrate that density directly impacts routability. Our findings provide valuable insights into how packing decisions affect FPGA efficiency and offer guidance for improving FPGA packing tools and architecture design by integrating interconnect-aware methods. The goal is to achieve efficient routing while maintaining an optimal balance between cluster density, CLB pin counts, and logical block sizes.

The complexity of interconnects is a critical, yet often underestimated, bottleneck in FPGA physical design. FPGA compilation is increasingly dominated by interconnect complexity, which limits routability and slows down placement and routing. We propose an interconnection-aware logic resynthesis flow that explicitly targets netlist structures with high fanout and interconnect congestion. We leverage local interconnection complexity metrics to guide resynthesis decisions. By allowing controlled node duplication and restructuring, our method improves logic locality and wireability at the expense of minor area overhead. Preliminary results show that this strategy can reduce routed wirelength and improve timing without changing the logic function, suggesting the potential to complement existing logic synthesis pipelines.

In the rapidly evolving domain of Photonic Integrated Circuits, reconfigurability is making strides through tunable waveguide elements, facilitating ‘general-purpose’ programmable waveguide grids. Routing in modern programmable photonic networks is challenging due to the numerous possibilities that exist for assigning photonic circuits in the grid. Especially the necessary scaling to devices with many more photonic elements calls for more advanced routing heuristics. We can leverage on the existing routers for electronic reconfigurable systems (FPGAs), such as the PathFinder. However, it is crucial to connect network elements while adhering to optical signals' physical restrictions. This complexity requires careful planning for smooth, error-free connections in the network infrastructure. This paper proposes a novel algorithm addressing routing challenges in programmable photonic circuits, specifically multicasting (single-source-multiple-sink) scenarios. Efficiently conserving the overall utilized routing resources stands as a crucial objective in programmable photonics routing. Our algorithm adeptly tackles multicasting routing problems with a particular focus on shortest pathlength multicasting routing. In contrast to the PathFinder, our algorithm demonstrates notable performance in optimization speed and the utilization of routing resources.

Deep Learning Large Language Models (LLMs) have the potential to automate and simplify code writing tasks. One of the emerging applications of LLMs is hardware design, where natural language interaction can be used to generate, annotate, and correct code in a Hardware Description Language (HDL), such as Verilog. This work provides an overview of the current state of using LLMs to generate Verilog code, highlighting their capabilities, accuracy, and techniques to improve the design quality. It also reviews the existing benchmarks to evaluate the correctness and quality of generated HDL code, enabling a fair comparison of different models and strategies.

Moore's Law has been guiding the development of the VLSI industry for the past half-century. This law underscores fabrication technology's crucial role in enhancing chip performance. However, with technology nearing physical limitations, we envisage that there is still significant potential for optimizing interconnection complexity in VLSI design. Interconnection complexity is characterized by Rent's Rule and the Rent exponent. We propose a new recursive normalized approach that can measure the Rent exponent accurately by eliminating the imbalance between blocks of different sizes. Then we demonstrate that optimizing the Rent exponent of the FPGA netlist can yield substantial benefits throughout the CAD flow process, particularly in physical design. By employing the GNL synthetic netlist generator to control interconnection complexity, we observe that a lower Rent exponent results in reduced running time, total wirelength and area usage. We also include real-world circuits from the Koios 2.0 benchmark suite in our analysis. The run-time of packing, placement and routing are ranging from exponential to double-exponential with respect to the Rent exponent. Our study highlights the significant impact of interconnection complexity on the EDA physical design flow. The results suggest that optimizing the netlist's interconnection structure during logic synthesis or packing to reduce complexity could enhance the efficiency and performance of the EDA flow.

In this presentation, Prof. Dirk Stroobandt will present a short overview of some of the major research results achieved in his research group at Ghent University. These include microreconfiguration as a fast run-time reconfiguration method, our newest FPGA placement and routing solutions, and recent work on multi-die architectures. However, his main focus will be on what future reconfigurable devices, architectures and tools should look like. The focus should be on mitigating interconnection delay and a strong interplay between technology, architectures and tools.

Interposer-based 2.5D FPGAs contain multiple dies interconnected through external wires. While essential for increasing capacity, these external connections introduce higher delays and longer wirelengths. Efficient placement tools are needed for such architecture to strategically manage signal counts at the die boundary. Previous research on 2.5D FPGA placement has often relied on global placement optimization, which, while effective, can be time-consuming and scales poorly with larger designs. Leveraging the modularity of 2.5D systems and the configuration of the interposer interface, we propose a novel approach to incorporating die-level parallelism that requires less global optimization. Our methodology employs netlist partitioning and introduces virtual anchor blocks to enable parallel placement of subcircuits on each die. We introduce a streamlined synchronization strategy for optimizing inter-partition nets. This methodology is integrated into the multi-die placement tool, ‘LiquidMD’, resulting in an enhanced parallelized version of the tool. Comparison of our base multi-die placer with a state-of-the-art tool that fully globally optimizes the placement demonstrates a significant runtime improvement without compromising placement quality. Additionally, we assess our partial synchronization technique in contrast to a placement strategy with no synchronization and observe improved critical path delay. Subsequently, we explore the synchronization process in-depth to assess how the placement can derive advantages from minimal synchronization. We initially evaluate the suitable position for introducing synchronization in the tool flow, followed by an assessment of the required synchronization frequency in the tool flow. Our research sheds light on determining the optimal balance between parallelism and synchronization in 2.5D FPGA placement, culminating in a modular placement algorithm that strikes a favourable balance between runtime efficiency and placement quality.

Interposer-based multi-die FPGAs (2.5D) are composed of multiple dies interconnected externally via wires, allowing the creation of FPGA systems with increased capacity. These external connections are generally fewer than the die's internal interconnection network and contribute to a higher delay and wirelength. These architectural limitations must be considered while optimizing PnR tools for multi-die solutions. The configuration of the interposer interface plays a crucial role in determining the routing resource availability at the die boundary and in ensuring congestion-free solutions. Interposer wires are generally designed to be thicker than the wires in the die's internal interconnection network, and their length can significantly impact overall delay. Longer interposer wires allow longer strides across the die, reducing the need for additional internal routing resources to handle cross-die net routing. Given these conflicting factors, it is crucial to determine an optimal length for the interposer wires. In this study, we aim to investigate how the length of the interposer wire influences the overall performance of PnR tools. We have developed a multi-die placer, LiquidMD and router, CRouteMD capable of accommodating various interposer lengths and have analyzed the impact of interposer length on the quality of PnR. Using a flexible interposer interface based on Xilinx's Virtex-7 architecture, we investigated wire lengths ranging from L12 to L48. In our comparison of PnR results across various interposer wire lengths, ranging from L12 to L48, we found that an optimal interposer wire length of approximately 14% of the die height (L30) improves the overall routing performance. This length of interposer wire reduces the CPD by 5% as compared to the longest interposer wire length which covers 22% of the die height.

Interposer-based 2.5D FPGAs contain multiple dies interconnected through external wires, which introduce higher delay and longer wirelength compared to the interconnection network of a single die. Efficient CAD tools are needed for such architectures to strategically manage signal counts at the die boundary. In this study, we introduce a modular approach for parallel die-level placement, eliminating the need for a time-consuming global placement optimization step. Our methodology uses netlist partitioning and adds virtual anchor blocks to enable parallel die placement and facilitate inter-partition net optimization. Our method results in a multi-die placement tool ‘LiquidMD’. Comparing our base multi-die placer with a state-of-the-art tool that fully globally optimizes placement shows sub-stantial runtime improvement with improved placement quality. We also introduce a synchronization strategy for optimizing inter-partition nets and assess how minimal synchronization benefits modular parallel placement. Our research results in a modular placement algorithm that strikes a favourable balance between runtime efficiency and placement quality.

Interposer-based multi-die FPGAs comprise multiple dies interconnected externally via wires, enabling the creation of FPGA systems with greater capacity. These external connections are fewer in number than the internal interconnection network of a die and they also contribute to increased delay and wirelength. These architectural shifts necessitate placement and routing tools to strategically reduce the count of signals at the die boundary. Multi-die FPGA systems also offer substantial potential for design modularity, where each die can be optimized for specific functionalities. Adapting EDA tools to leverage these inherent device characteristics is imperative. Additionally, the modular nature of the system paves the way for parallelized implementations. Previous studies on multi-die FPGA placement have primarily concentrated on reducing signal crossings across die boundaries via global optimization. This strategy, however, incurs significant runtime demands, as it treats the multi-die FPGA as a unified fabric. This study presents a new methodology to partition and parallelize placement within a multi-die architecture. Our approach facilitates the optimization of partitioned nets without the reliance on a global optimization step. With netlist partitioning and adding virtual anchor blocks, the subcircuits can be placed on each die in parallel. The multi-die placer algorithm is integrated into the fast analytical placement tool 'Liquid'. A comprehensive performance comparison of our multi-die placer with the single-die monolithic implementation unveils similar quality results with improved runtime efficiency. Lastly, we compare our strategy to the widely-used academic placer, VPR, which relies on global optimization. The results demonstrate a 42x enhancement in runtime for lower estimations of Total Wire-length (TWL) and Critical Path Delay (CPD).

Electronic Design Automation (EDA) for Field Programmable Gate Arrays (FPGAs) strives to optimize the timing properties of physical circuits on FPGAs. The process involves logic synthesis and packing in physical synthesis, which generates a circuit graph. This graph is subsequently placed and routed onto the FPGA architecture to create a physical circuit. Researchers have demonstrated that merely minimizing circuit size does not necessarily lead to an optimal wirelength. Namely, as circuit size decreases the interconnection complexity can (and normally does) increase. This work focuses on gaining a better understanding of this phenomenon. We investigate the trade-off between size and interconnection complexity by examining ideal circuit graphs which are an abstraction of real circuits graphs based on Rent's rule. An ideal circuit is reduced to only three parameters: size Bc, interconnection complexity r and terminals per block K. First we study the effect of size Bc and interconnection complexity r on wirelength by making a visual representation with Donath's wirelength prediction method. The created visual clearly exposes and provides insight in the tradeoff between size and interconnection complexity. Furthermore, it shows that interconnection complexity is limited subject to circuit size. Second, we derive the shape of ideal circuit graphs based on its three parameters. We use the hypervolume-hyperarea interpretation of Rent's rule as a basis for constructing ideal circuit graphs. In understanding the structure of ideal circuit graphs it becomes clear why complexity is bound by size. We find that the complexity r of an ideal circuit is lower than log3(Bc)−1/log3(Bc). The model for building ideal circuit graphs enhances our intuitive understanding of interconnection structure in FPGA circuits and might be the basis for a new synthetic benchmark generation technique.

Lossy compression solutions have grown up during the past decades because of the increment of the data rate in the new-generation hyperspectral sensors; however, linear compression techniques include useless information on regions of little interest for the final application and, at the same time, scarce information on areas of interest. In this article, a transform-based lossy compressor, HyperLCA, has been extended to include a runtime adaptive distortion feature that brings multiple compression ratios in the same scenario. The solution has been designed to keep the same hardware-friendly feature, just as its previous version, specifically conceived to ease the deployment of the solution on reconfigurable hardware devices (FPGAs). The experiments demonstrate that the new version of the compressor is able to process 1024 × 1024 hyperspectral images and 180 spectral bands (377.5 MB) in 0.935 s with a power consumption of 1.145 W. In addition, experimental results also reveal that our architecture features high throughput (MSamples/s) and remarkable energy-efficiency (MB/s/W) tradeoffs, $10\times$ and $6\times$ greater than the best state-of-the-art solution, respectively.

High-capacity multi-die FPGA systems generally consist of multiple dies connected by external interposer lines. These external connections are limited in number. Further, these connections also contribute to a higher delay as compared to the internal network on a monolithic FPGA and should therefore be sparsely used. These architectural changes compel the placement & routing tools to minimize the number of signals at the die boundary. Incorporating a netlist partitioning step in the CAD flow can help to minimize the overall number of signals using the cross-die connections. Conventional partitioning techniques focus on minimizing the cut edges at the cost of generating unequal-sized partitions. Such highly unbalanced partitions can affect the overall placement & routing quality by causing congestion on the denser die. Moreover, this can also negatively impact the overall runtime of the placement & routing tools as well as the FPGA resource utilization. In previous studies, a low value of the unbalance was proposed to generate equal-sized partitions. In this work, we investigate the factors that influence the netlist partitioning quality for a multi-die FPGA system. A die-level partitioning step, performed using hMETIS, is incorporated into the flow before the packing step. Large heterogeneous circuits from the Koios benchmark suite are used to analyze the partitioning-packing results. Consequently, we examine the variation in output unbalance, the number of cut edges vs the input value of unbalance. We propose an empirical optimal parametric value of the unbalance factor for achieving the desired partitioning quality for the Koios benchmark suite.

High-capacity multi-die FPGA systems generally consist of multiple dies connected by external interposer lines. These external connections are limited in number. Further, these connections also contribute to a higher delay as compared to the internal network on a monolithic FPGA and should therefore be sparsely used. These architectural changes compel the placement & routing tools to minimize the number of signals at the die boundary. Incorporating a netlist partitioning step in the CAD flow can help to minimize the overall number of signals using the cross-die connections.

cREAtIve targets the development of novel highly-adaptable embedded deep learning solutions for automotive and traffic monitoring applications, including position sensor processing, scene interpretation based on LiDAR, and object detection and classification in thermal images for traffic camera systems. These applications share the need for deep learning solutions tailored for deployment on embedded devices with limited resources and featuring high adaptability and robustness to changing environmental conditions. cREAtIve develops knowledge, tools and methods that enable hardware-efficient, adaptable, and robust deep learning.