Self-aligned triple patterning (SATP) technique offers both improved resolution and quasi-2D design flexibility for scaling integrated circuits down to sub-15nm half pitch. By implementation of active layout decomposition/synthesis using mandrel and spacer engineering, SATP process represents a prospective trend that not only drives up the feature density, but also breaks the 1-D gridded limitations posed to future device design. In this paper, we shall present the research progress made in optimizing SATP process to improve its lithographic performance. To solve the previously reported difficulties in etching small mandrels and removing sacrificial spacers, new materials are tested and a promising scheme (using oxide as the mandrel and poly/amorphous Si as the sacrificial spacer) is identified. In the new process, a diluted HF process is applied to shrink the mandrel (oxide) line CD and a highly selective dry etch (which does not attack the mandrel and structural spacer) is developed to strip the sacrificial Si spacers, resulting in significantly improved process performance. We also address the issue of reducing SATP process complexity by exploring the feasibility of a 2-mask concept for specific types of layout.
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