In this paper, we present a thorough investigation of self-aligned octuple patterning (SAOP) process characteristics, cost structure, integration challenges, and layout decomposition. The statistical characteristics of SAOP CD variations such as multi-modality are analyzed and contributions from various features to CDU and MTT (mean-to-target) budgets are estimated. The gap space is found to have the worst CDU+MTT performance and is used to determine the required overlay accuracy to ensure a satisfactory edge-placement yield of a cut process. Moreover, we propose a 5-mask positive-tone SAOP (pSAOP) process for memory FEOL patterning and a 3-mask negative-tone SAOP (nSAOP) process for logic BEOL patterning. The potential challenges of 2-D SAOP layout decomposition for BEOL applications are identified. Possible decomposition approaches are explored and the functionality of several developed algorithm is verified using 2-D layout examples from Open Cell Library.

A quasi two-dimensional analytic model for trapezoidal fin field-effect transistors (FinFETs) with non-uniform doping profiles is developed. The perturbation method, combined with a variable transformation technique, is applied to solve the nonlinear Poisson’s equation analytically. Our approach lumps the depletion and inversion terms together to capture the effects of nonlinear coupling and spatial variation of an arbitrary doping profile. Trapezoidal boundary conditions are reformulated accordingly and a continuous analytic current–voltage (I–V) model for doped trapezoidal FinFETs is derived. More accurate prediction of the surface potential and the I–V characteristics is achieved by setting the operating point of a Taylor expansion at the channel surface and introducing the higher-order correction. The short-channel effect is also studied and verified with technology computer-aided design (TCAD) simulations, which indicates a high accuracy of this new model.

Self-aligned quadruple patterning (SAQP) process is a proven technique for deep nano-scale IC manufacturing, while its mask design and layout decomposition strategy is less intuitive. In this paper, we examine both 2- and 3-mask SAQP process characteristics and develop various decomposition methods to achieve higher feature density and 2-D design flexibility. It is demonstrated that by generating assisting mandrels, SAQP layout decomposition can be degenerated into a SADP decomposition problem for which mature algorithms already exist in our EDA industry. Moreover, a spacer-expansion mask concept is introduced and a grouping/coloring algorithm to assign feature colors is developed for 3-mask SAQP layout decomposition. Finally, several 2-D layouts are successfully decomposed, showing the functionality of the decomposition method we proposed.

An analytic current–voltage (I–V) model for doped double-gate metal–oxide–semiconductor field-effect transistors (MOSFETs) is derived by using a rigorous perturbation method to solve one-dimensional (1D) Poisson's equation. More accurate prediction of the surface potential and I–V characteristics is achieved by introducing a higher-order correction and setting the operating point of Taylor expansion at the channel surface where the major population of mobile charge is located. Both technology computer-aided design (TCAD) simulations and the numerical solution to 1D Poisson's equation verify the improved accuracy of our model compared with Berkeley short-channel insulated-gate FET model (BSIM) model, especially when the gate voltage and doping level are higher. We also discuss and compare the numerical errors caused by the approximations made in BSIM and our models.

Self-aligned sextuple patterning (SASP) is a promising technique to scale down the half pitch of IC features to sub-10nm region. In this paper, the process characteristics and decomposition methods of both positive-tone (pSASP) and negative-tone SASP (nSASP) techniques are discussed, and a variety of decomposition rules are studied. By using a node-grouping method, nSASP layout conflicting graph can be significantly simplified. Graph searching and coloring algorithm is developed for feature/color assignment. We demonstrate that by generating assisting mandrels, nSASP layout decomposition can be degenerated into an nSADP decomposition problem. The proposed decomposition algorithm is successfully verified with several commonly used 2-D layout examples.

Self-aligned multiple patterning (SAMP) techniques can potentially scale integrated circuits down to half-pitch 7nm. In this paper, we present a comparative analysis of self-aligned quadruple (SAQP) and sextuple (SASP) techniques by investigating their technological merits and limitations, process complexity and cost structures, strategy of layout decomposition/synthesis, and yield impacts. It is shown that SASP process complexity is comparable to that of SAQP process, while it offers 50% gain in feature density and may be extended for one more node. The overlay yield of cut process is identified to be a challenge when the minimum device feature is scaled to half-pitch 7nm. The mask design issues for various applications using each technique are discussed, and the corresponding layout decomposition/synthesis strategy for complex 2D patterning is proposed. Although the high-dose EUV single-cut process can save significant costs when applied to replace the 193i multiple-cut process to form fin/gate structures, our cost modeling results show that SADP+EUV approach is still not cost effective for patterning other critical layers that generally require the same mask number (and lithographic steps) as the non-EUV schemes.

Spacer based self-aligned multiple patterning (SAMP), when combined with 193nm immersion or EUV lithography, can potentially drive the resolution of IC features down to 5-nm half pitch. By designing various mandrel patterns which further define the route of the following spacers, some SAMP techniques are more capable of driving up the feature density, while some others are favorable to reduction of process complexity by using fewer masks and allowing 2-D design flexibility. In this paper, we shall present a general analysis of several key issues of SAMP techniques: resolution capability, process complexity, overlay requirement, and performance.

As promising paths to break the diffraction limit of optical lithography, several self-aligned multiple patterning (SAMP) techniques have been proposed to improve the resolution capability recently. In this paper, we show that SATP (selfaligned triple patterning) process variations differ significantly from conventional optical lithography process. It is found that mandrels fabricated by a SATP process usually come up with worse line-width roughness (LWR) and critical-dimension uniformity (CDU) than spacers do. In addition to that, the gap space between two neighboring spacers is often accompanied with a poor CDU. Similar to SATP process, the self-aligned quadruple patterning (SAQP) technique also brings its own characteristics of process variability along with the scaling capability. SAMP process variability (such as intra-cell variability and process multi-modality) and their impacts on device performance of the multiple-gate MOSFETs are discussed. Moreover, we develop an analytic double-gate MOSFET model to study the effects of LWR on both fin thickness and gate misalignment. Numerical simulations are carried out to verify the accuracy of our simplified model. This analytic approach provides an efficient method for compact modeling of LWR induced device variations.

Self-aligned triple patterning (SATP) technique offers both improved resolution and quasi-2D design flexibility for scaling integrated circuits down to sub-15nm half pitch. By implementation of active layout decomposition/synthesis using mandrel and spacer engineering, SATP process represents a prospective trend that not only drives up the feature density, but also breaks the 1-D gridded limitations posed to future device design. In this paper, we shall present the research progress made in optimizing SATP process to improve its lithographic performance. To solve the previously reported difficulties in etching small mandrels and removing sacrificial spacers, new materials are tested and a promising scheme (using oxide as the mandrel and poly/amorphous Si as the sacrificial spacer) is identified. In the new process, a diluted HF process is applied to shrink the mandrel (oxide) line CD and a highly selective dry etch (which does not attack the mandrel and structural spacer) is developed to strip the sacrificial Si spacers, resulting in significantly improved process performance. We also address the issue of reducing SATP process complexity by exploring the feasibility of a 2-mask concept for specific types of layout.

An experimental study and modeling of double-surrounding-gate (DSG) and silicon-on-nothing surrounding-gate (SONSG) MOSFETs are presented. The manufacturing challenges of advanced multiple-gate MOSFETs are discussed; and DSG and SONSG devices are proposed as potential solutions to overcome these fabrication challenges. The analytic general solution to cylindrical (nonlinear) Poisson's equation is applied to analyze DSG and SONSG device performance. Numerical issues of solving two coupled implicit transcendental equations to obtain two integration constants are addressed. It is found that under the same boundary conditions, concentration of the induced charge in a DSG MOSFET is comparable to a conventional double-gate MOSFET.

Spacer based self-aligned multiple patterning (SAMP) techniques potentially allow us to scale integrated circuits down to sub-10nm half pitch with no need of EUV lithography. In this paper, we shall present a general analysis of technological merits, process complexity and costs of various SAMP techniques. It is shown that some SAMP techniques such as self-aligned quadruple/sextuple patterning (SAQP/SASP) are more capable of increasing the pattern density, while self-aligned triple patterning (SATP) is more beneficial to reducing process complexity by allowing quasi-2D IC design and requiring fewer masks. Besides their different scaling/resolution capability and process challenges, each SAMP technique is accompanied with unique characteristics of CD uniformity (CDU) and line-width roughness (LWR), which indicates their application areas and the related IC design/fabrication methodologies vary significantly by industry segment. Process costs of various self-aligned multiple patterning schemes are calculated, which show that within the common resolution capability, SATP technique is the most cost effective while the EUV+SADP approach only offers limited benefits.

A hybrid self-aligned triple and negative-tone double patterning (HTDP) technique is proposed to achieve improved resolution and quasi-2D IC design flexibility at lower cost. Critical challenges of HTDP process and its key design issues such as overlay, layout decomposition and synthesis are investigated, and possible design solutions are discussed. It is shown that using mandrel (including assisting mandrel) and spacer engineering, HTDP on-grid layout design is a promising approach to break the limitation of 1-D gridded design. Efficient formulation of HTDP layout decomposition/synthesis into a Boolean satisfactory problem is demonstrated. Moreover, by considering geometric constraints of HTDP layout and several process related assumptions, it is possible to significantly reduce the number of layout features and Boolean input variables. Several examples of 2-D layout are used to demonstrate the process of HTDP decomposition/synthesis, as well as the simplification of its algorithm to reduce runtime. Specifically, preliminary results from implementation of a 2-mask HTDP design for patterning a 2-D dense line/space array with pads are reported.