The continuous drive toward the miniaturization of Integrated Circuits (ICs) is pushing the physical boundaries of device scaling. As transistor gate and interconnect dimensions shrink, several challenges emerge, including increased power density, thermal dissipation constraints, and quantum effects. Among these, electromigration—caused by the momentum transfer from high current densities to atoms—results in the displacement of material within interconnects, potentially leading to unintended open circuits or shorts. Similarly, manufacturing defects, environmental stresses, and aging effects further exacerbate these reliability issues, often manifesting as permanent faults, such as logic stuck-at-0 or stuck-at-1 conditions. To address these issues, Design-for-Test (DFT) infrastructure and Software-Based Self-Test (SBST) have been developed. While DFT is expensive in terms of area and performance, SBST is a cost-effective alternative that uses processor resources to test the chip. However, generating efficient test patterns with high fault coverage remains a challenge. In this paper, we propose a technique for optimizing testing software for SBST targeted towards specific components with uniform structures such as a RISC-V Register File. The method requires knowledge of the component structure and function, and uses fault simulation to verify fault coverage. The method achieved a fault coverage of 99% of functionally testable faults in the Register File.
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