POWER10™: A 16-Core SMT8 Server Processor with 2tb/s Off-Chip Bandwidth in 7nm Technology

The POWER10™ processor designed for enterprise workloads contains 16 synchronous SMT8 cores (Fig. 2.4.1) coupled through a bi-directional high-bandwidth race-track [1] [2]. A SMT8 core with its associated cache is called a core chiplet, and a pair of core chiplets forms a 39.4mm2 design tile. Designed in a 7nm bulk technology, the 602mm2 chip (0.85× of POWER9™ [3]) has nearly 18B transistors, 110B vias and 20 miles of on-chip interconnect distributed across 18 layers of metal: 8 narrow-width layers for short range routes, 8 medium-width layers for high performance signals and two 2160nm ultra-thick metal (UTM) layers dedicated for power and global clock distribution. There are 10 input voltages as shown in Fig. 2.4.1: core/cache logic (Vdd), cache arrays (Vcs), nest logic (Vdn), two PHY voltages (Vio, Vpci), stand-by logic (Vsb), a high-precision reference voltage (Vref), DPLL voltage (VDPLL), analog circuitry voltage (VAVDD), and an interface voltage (V3P3). The C4 array contains 24477 total connections (1.25× of [3]) with 10867 power, 11879 ground and 1731 signal connections. A core and its associated L2 cache are power-gated together, while the L3 cache is power-gated independently.