The paper presents a 16Gb SDRAM with a vertical-channel-transistor-based 4F(2) cell and cell-on-peripheral (COP) architecture. Wafer-to-wafer hybrid copper bonding is applied to COP, which increases the total die count per wafer by more than 20% with the same design rules. Fabricated in a 10nm-class DRAM process, the test chip performs read and write operations successfully, opening the possibility for further DRAM-technology scaling.
Conventional management of type-1 diabetes (T1D) relies on finger-prick blood sampling or electrochemical methods, which prevent continuous monitoring and treatment. This paper presents a novel epidermal pasting bioelectronic device (PBD). The device integrates a 19fA-resolution bioluminescence analog front-end (BAFE) with TDM-SAR calibration and a hybrid-mode LED driver. It enables closed-loop realtime detection and precision treatment for T1D. The battery life reaches 48 days.
This paper presents a single-transformer multi-output isolated DC-DC converter generating three regulated rails $(+15 ~\mathrm{V},-5 ~\mathrm{V}$, and +5 V) from wide $12 / 24 ~\mathrm{V}$ inputs. By sharing a common secondary winding in a dual-doubler rectifier configuration, the design achieves three outputs using only four power transistors. Additionally, a reconfigurable two-mode inverter ensures high efficiency across both input voltage conditions. The converter reaches a peak efficiency of 68% with maximum output power of 2.5W.
This paper presents edge-triggered transceivers (ETT), enabling a 32Gb UCle-like chiplet interconnect when integrated within an active local silicon interconnect (aLSI). The ETT achieves power consumption of 0.07pJ/b and supports compact top-die TX/RX designs while optimizing 0.36pJ/b energy efficiency and 12.35Tb/s/mm2 area bandwidth density. It demonstrates a 32Gb/s die-to-die link at 0.75V with 20.46ps eye width (65% UI) and 530mV eye height across 64 lanes in a 3nm CMOS process.
Diverse AI workloads require flexible data representations and numerical formats. In this work, we present a reconfigurable 2's-complement and sign-magnitude scheme integrated within a versatile-format CIM macro supporting MX, LNS, FP, and INT for MAC operations. Implemented in a 16 nm 72 kb gain-cell array, the macro achieves record energy efficiency (120.5TFLOPS/W) and throughput density $(3.18 \text{TOPS} / \text{mm} 2)$ in MXINT8 mode.
This work presents a high-precision, power-efficient Class-D audio amplifier (CDA) that addresses switching losses and reconfiguration-induced nonlinearity through neural-network-assisted pre-reconfiguration. Consequently, this CDA achieves the lowest THD+N of −108.2 dB and a very high $\text{FoM}_{\text{THD+N }}$ of 3747, corresponding to a 48% improvement over the state-of-the-art in the accompanying comparison table. This CDA also attains an ultralow quiescent current of 0.64 mA and highest efficiency of 66% at 10 mW.
This work presents an 8-lane $112 ~\text{Gb} / \mathrm{s} /$ wire single-ended simultaneous bi-directional transceiver with a 3mm shield-less on-chip channel. A dynamic equalizer is proposed to decouple the bi-directional signals, and compensate for insertion loss and crosstalk. Fabricated in 28nm CMOS, the transceiver achieves a BER of less than 10−14, and an energy efficiency of $1.01 \text{pJ} / \mathrm{b}$.
A 112Gb/s PAM-4 simultaneous bidirectional (SBD) transceiver in 28nm CMOS is presented. It features a hybrid with a 2xVDD stacked driver to restore signal swing, a joint delay and slew-rate matching scheme to eliminate dynamic glitches, and a two-step echo canceller to mitigate reflections. The transceiver achieves BER < 1E-10 over a 12.7dB loss channel (equivalent to 24.4dB at Nyquist), with 1.73pJ/b energy efficiency and an FoM of 0.14pJ/b/dB.
This work demonstrates a UCIe-S compliant die-to-die PHY at 48Gb/s/lane across 16 lanes, achieving 1.24Tb/s/mm shoreline BW density over a 30mm organic package at 1.2pJ/b, extendable to 56GT/s (1.13pJ/b). Circuit innovations include an impedance-invariant TX CTLE, high-swing N/N driver, compact resonant clocking, double-tail latch w/ improved setup/hold times, and common-mode supply-noise rejection. Compared to prior UCIe-S, it achieves 3x higher data rate and 2.8x higher BW density.
A multi-modal end-to-end driving processor is proposed with 4 features: 1) a sparsity reasoning unit to maximize sparsity exploitation, 2) a flexible sparse-dense heterogeneous architecture with a sparsity-aware adaptive core orchestrator to maximize core utilization, 3) an energy-efficient segmented aggregation network, and 4) a long-/short-term memory unit to minimize external memory access (EMA) of temporal attention. It achieves 10.3fps at 71.3 mJ/frame, consuming 218× less energy than a state-of-the-art driving SoC.
In this work, an NPN-based temperature sensor is presented that introduces a backgroundcalibration scheme to correct all current-domain errors in its front-end. It achieves an inaccuracy of 0.05° C(3 \sigma) from −70° C to 125° C (RIA=0.05%) after a one-point trim, which represents the state-of-the-art energy efficiency (100fJ.K2) and power supply sensitivity (PSS) (0.004°C/V).
Prior works on physical-layer eavesdropping protection only addressed off-axis Eve. This paper presents the first TX to defend against both main-beam and off-axis Eves. Incorporating three key components: frequency-diverse sub-arrays, secret phase keys, and antenna subset modulation, the 28 GHz TX demonstrates highly scrambled constellations for all Eves, while the legitimate RX's reception remains intact ($\sim 6 \% \text{EVM}_{\text {rms }}$), with only 2% DC power overhead compared to a standard phased-array TX.
This work presents a 55nm speculative decoding-based LLM accelerator with bumping-based face-to-face ReRAM-on-logic stacking technology. It features a local rotation unit for outlier-free low-bit quantization, a stacking-aware PNM architecture co-designed with blockwise vector quantization to reduce weight EMA overheads, and an adaptive parallel speculative decoding scheme with an out-of-order scheduler for high resource and bandwidth utilization. Our chip achieves 14.08-to-135.69token/s and 4.46-to-7.17x speedup over vanilla speculative decoding.
The AI supercycle is rapidly increasing demand for compute performance and scalability across all levels, from data centers to edge devices. By 2030, the semiconductor total addressable market (TAM) is projected to reach $1.2T with electronic systems at $5.2T. With silicon designs surpassing 200 billion transistors and chiplet-based architectures becoming common, traditional electronic-design-automation (EDA) workflows are insufficient. This plenary discusses how agentic AI can be applied to complex silicon and system design tasks through multi-agent orchestration and iterative reasoning, outlining a framework for its use in EDA solutions, highlighting some of the challenges, and exploring future directions. From optimizing power, performance, and area of silicon to managing data centers, AI-powered solutions are critical for the engineers designing the next generation of AI infrastructure.
Quantum computing is advancing rapidly, offering the potential to transform computational paradigms and tackle problems that are intractable for classical systems. Realizing practical quantum systems demands the development of an entirely new computing stack—from qubits and quantum processors to components, wiring and control electronics, transpilers, error handling, software, algorithms, and the compute architecture to integrate quantum and classical resources at scale. This plenary will provide an overview of the current state of quantum computing and outline the milestones on the path toward building a large-scale, fault-tolerant quantum computer by 2029. The significant improvements in hardware, software, and system integration, pushing the performance of quantum computing to reach quantum utility and advance toward quantum advantage, will be presented. Breakthroughs in error correction and a modular approach indicated in the IBM Quantum Roadmap outline a clear path to quantum systems using 200 logical qubits and 100 million quantum operations by 2029 and 2,000 logical qubits a few years later. Furthermore, advances in quantum algorithms, combined with the integration of quantum systems and high-performance computing (HPC), will unlock powerful synergies—accelerating the timeline for applications previously considered to be far in the future.
The paper presents a 256 -channel solid-state nanopore readout IC in 65 nm CMOS. A new integrate-and-hold TIA cuts per-pore power and area $>6 \times$ while achieving 1 MHz BW and 193 pArms at 10 nA. Event detection with dynamic slot allocation exploits sub-1 percent activity to reduce ADC data $32 \times$. The chip delivers 1 mW and 0.019 mm2 per pore and records labeled DNA translocations, enabling scalable, low-cost single-molecule diagnostics.
We present a two-stage FEC decoder that combines soft-decision Chase decoding with order-1 ordered statistics decoding, offering robust error correction for URLLC. A 1.1 mm2, 16 nm decoder prototype with optimized Gaussian elimination and early exits achieves an average latency of 14.4 ns and a worst-case latency of 132.6 ns, improving upon prior work by $53 \times$ and five orders of magnitude, respectively. The prototype delivers 15.2 Gbps at 13.1 pJ/b, outperforming state-of-the-art URLLC FEC decoders.
A quantum-inspired analog variable k-SAT solver supporting up to 200 variables and 1016 clauses. Enabling techniques include make/break feedback, distributed k-SAT logic, digital macro coupling, and feedback optimization. The 28nm CMOS prototype achieves a 4.92 mu s mean solution time and a 19.1nJ mean energy consumption for 50-variable 3-SAT problems with 100% solvability and accuracy, representing 3.5x and 3x improvements in energy and solution time respectively, compared to the state-of-the-art.
We report a $54 \times 42$-resolution SPAD-based LIDAR receiver SoC leveraging 3D-stacked $65 / 40 ~\text{nm}$ technology with high-frequency TDC and 2 counters for ToF and intensity exposure, with peripheral memories used for image signal processing (ISP) frame stores, point cloud generation & HDR management. A hybrid on-chip & package-embedded 25V boost converter is described integrating SPAD supply generation synchronized with sensor frame timing. The sensor is integrated in a LIDAR module for 9.6m ranging with <1cm error.
State-space models (SSMs) and weight-only quantization alleviate huge external memory access with a minimal accuracy degradation. To support both efficiently, we propose LUTSSM, a LUT-based SSM accelerator with a many-to-many LUT-ACC and an element-wise (EW) layer fusion. LUT-SSM efficiently supports INT-FP GEMM and sequential EW operations in the SSM blocks. Fabricated in 28nm FD-SOI, LUT-SSM achieves 99.3TFLOPS/W peak efficiency and 96.1TFLOPS/W on Mamba 1.4B, improving energy efficiency by $1.28 \times$ over recent designs.
