Recent Progress on Multipatterning: Approach to Pattern Placement Correction

Multi-patterning technology using 193nm immersion lithography has been used since the 22nm logic node generation and it appears that it will continue to be used as far as the 14nm generation. At the same time, the industry trend is to simplify pattern design and reduce complexity in lithography though single directional (1D) layout[1]. On the other hand, there is increasing concern about pattern placement error in the application of this technology. This paper focuses on pattern placement variation in the process steps of pattern formation in 1D layout design, presents the results of a study on the effects of factors other than overlay accuracy on microscopic behavior, and describes techniques for improving pattern placement.