For self-aligned multiple patterning, higher etch selectivity between mandrel and spacer is desired to lessen roughness, and thereby prevent pitch walk. We selected dual carbon layers as mandrels and silicon oxide films as spacers for a new self-aligned quadruple patterning process since they potentially provide infinite etch selectivity. We gained insolubility and etch selectivity between two carbon layers by infiltrating trimethylsilyldimethylamine into one of the carbon layers under the ambient atmosphere. Significantly, neither necking nor recess were observed when the spin-on-glass anti-reflective coating was removed. Thus, a SAQP scheme was developed and successfully demonstrated a sub15-nm half-pitch pattern. Additionally, this scheme improves affordability since all the processes can be performed in the ambient pressure within a coater module.

Extreme UV(EUV) technology must be potential solution for sustainable scaling, and its adoption in high volume manufacturing(HVM) is getting realistic more and more. This technology has a wide capability to mitigate various technical problem in Multi-patterning (LELELE) for via hole patterning with 193-i. It induced local pattern fidelity error such like CDU, CER, Pattern placement error. Exactly, EUV must be desirable scaling-driving tool, however, specific technical issue, named RLS (Resolution-LER-Sensitivity) triangle, obvious remaining issue. In this work, we examined hole patterning sensitizing (Lower dose approach) utilizing hole patterning restoration technique named "CD-Healing" as post-Litho. treatment.

Gridded design rules([1]) is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line&space pattern by using multiple patterning techniques such as self-aligned multiple patterning (SAMP) and litho-etch-litho-etch (LELE)([2][3][4]). On the other hand, Line cut process has some error parameters such as pattern defect, placement error, roughness and X-Y CD bias with the decreasing scale. We tried to cure hole pattern roughness to use additional process such as Line smoothing([5]). Each smoothing process showed different effect. As the result, CDx shrink amount is smaller than CDy without one additional process. In this paper, we will report the pattern controllability comparison of EUV and 193-immersion. And we will discuss optimum method about CD bias on hole pattern.

Both local variability and optical proximity correction (OPC) errors are big contributors to the edge placement error (EPE) budget which is closely related to the device yield. The post-litho contact hole healing will be demonstrated to meet after-etch local variability specifications using a low dose, 30mJ/cm2 dose-to-size, positive tone developed (PTD) resist with relevant throughput in high volume manufacturing (HVM). The total local variability of the node 5nm (N5) contact holes will be characterized in terms of local CD uniformity (LCDU), local placement error (LPE), and contact edge roughness (CER) using a statistical methodology. The CD healing process has complex etch proximity effects, so the OPC prediction accuracy is challenging to meet EPE requirements for the N5. Thus, the prediction accuracy of an after-etch model will be investigated and discussed using ASML Tachyon OPC model.

Lithographic scaling continues to advance by extending the life of 193nm immersion technology, and spacer-type multi-patterning is undeniably the driving force behind this trend. Multi-patterning techniques such as self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP) have come to be used in memory devices, and they have also been adopted in logic devices to create constituent patterns in the formation of 1D layout designs. Multi-patterning has consequently become an indispensible technology in the fabrication of all advanced devices. In general, items that must be managed when using multi-patterning include critical dimension uniformity (CDU), line edge roughness (LER), and line width roughness (LWR). Recently, moreover, there has been increasing focus on judging and managing pattern resolution performance from a more detailed perspective and on making a right/wrong judgment from the perspective of edge placement error (EPE). To begin with, pattern resolution performance in spacer-type multi-patterning is affected by the process accuracy of the core (mandrel) pattern. Improving the controllability of CD and LER of the mandrel is most important, and to reduce LER, an appropriate smoothing technique should be carefully selected. In addition, the atomic layer deposition (ALD) technique is generally used to meet the need for high accuracy in forming the spacer film. Advances in scaling are accompanied by stricter requirements in the controllability of fine processing. In this paper, we first describe our efforts in improving controllability by selecting the most appropriate materials for the mandrel pattern and spacer film. Then, based on the materials selected, we present experimental results on a technique for improving etching selectivity.

Multi-patterning has been adopted widely in High volume manufacturing as 193 immersion extension, and it becomes realistic solution of nano-order scaling. In fact, it must be key technology on single directional (1D) layout design [1] for logic devise and it becomes a major option for further scaling technique in SAQP. The requirement for patterning fidelity control is getting savior more and more, stochastic fluctuation as well as LER (Line edge roughness) has to be micro-scopic observation aria.In our previous work, such atomic order controllability was viable in complemented technique with etching and deposition [2]. Overlay issue form major potion in yield management, therefore, entire solution is needed keenly including alignment accuracy on scanner and detectability on overlay measurement instruments. As EPE (Edge placement error) was defined as the gap between design pattern and contouring of actual pattern edge, pattern registration in single process level must be considerable. The complementary patterning to fabricate 1D layout actually mitigates any process restrictions, however, multiple process step, symbolized as LELE with 193-i, is burden to yield management and affordability. Recent progress of EUV technology is remarkable, and it is major potential solution for such complicated technical issues. EUV has robust resolution limit and it must be definitely strong scaling driver for process simplification. On the other hand, its stochastic variation such like shot noise due to light source power must be resolved with any additional complemented technique.In this work, we examined the nano-order CD and profile control on EUV resist pattern and would introduce excellent accomplishments.

The continuously scaling of complex device geometries is driving by the self-aligned multiple patterning techniques. Depending on such simplified LS scaling, FinFET design rule has been accelerated to unidirectional design layout. [1] In particular Fin, Gate and Metal layers are based on grating with cutting/blocking scheme, these process have become high volume manufacturing techniques in N14 and beyond.[2,3] On the other hand, immersions based pitch scaling of contact hole, via and cutmask processes are required multiple lithography and etching passes.[4] Overlay management is not only the overlay accuracy of layer to layer, to determine the placement error and patterning fidelity in single layer. In this work, focusing on the placement in hole pattern, total placement error budget will be discussed from the viewpoints of metrology, inspection, Mask, OPC and wafer processing. In addition, hole shrink and hole healing techniques have more significant factors in terms of design-process technology co-optimization for N7 and beyond.[5]

One of the practical candidates to produce 7nm node logic devices is to use the multiple patterning with 193-immersion exposure. For the multiple patterning, it is important to evaluate the relation between the number of mask layer and the minimum pitch systematically to judge the device manufacturability. Although the number of the time of patterning, namely LE(Litho-Etch) boolean AND x-time, and overlay steps have to be reduced, there are some challenges in miniaturization of hole size below 20nm. Various process fluctuations on contact hole have a direct impact on device performance. According to the technical trend, 12nm diameter hole on 30nm-pitch hole will be needed on 7nm node. Extreme ultraviolet lithography (EUV) and Directed self-assembly (DSA) are attracting considerable attention to obtain small feature size pattern, however, 193-immersion still has the potential to extend optical lithography cost-effectively for sub-7nm node. The objective of this work is to study the process variation challenges and resolution in post-processing for the CD-bias control to meet sub-20nm diameter contact hole. Another pattern modulation is also demonstrated during post-processing step for hole shrink. With the realization that pattern fidelity and pattern placement management will limit scaling long before devices and interconnects fail to perform intrinsically, the talk will also outline how circle edge roughness (CER) and Local-CD uniformity can correct efficiency. On the other hand, 1D Gridded-Design-Rules layout (1D layout) has simple rectangular shapes. Also, we have demonstrated CD-bias modification on short trench pattern to cut grating line for its fabrication.

Gridded design rules[1] is major process in configuring logic circuit used 193-immersion lithography. In the scaling of grid patterning, we can make 10nm order line and space pattern by using multiple patterning techniques such as self-aligned multiple patterning (SAMP) and litho-etch- litho-etch (LELE)[2][3][5] . On the other hand, Line cut process has some error parameters such as pattern defect, placement error, roughness and X-Y CD bias with the decreasing scale. Especially roughness and X-Y CD bias are paid attention because it cause cut error and pattern defect. In this case, we applied some smoothing process to care hole roughness[4]. Each smoothing process showed different effect on X-Y CD bias. In this paper, we will report the pattern controllability comparison of trench and block + inverse. It include X-Y CD bias, roughness and process usability. Furthermore we will discuss optimum method focused on X-Y CD bias when we use additional process such as smoothing and shrink etching .

Through the continuous scaling with extension of 193-immersion lithography, the multi-patterning process with the grid-based design has become nominal process for fine fabrication to relax tight pitch designs [1] . In self-aligned type multiple patterning, 7 nm node gate pattern was reported [2],[3] and it was become a focal point LER on core-pattern is essential category to control pattern placement variations. Though CD uniformity (CDU) on line pattern in self-aligned double patterning (SADP) is relatively stable caused in high thickness controllability of spacer deposition films, the variations of CDU and LER on first core pattern impinge the CDU on space and pitch pattern. In previous study, pattern fidelity of single exposure patterning was improved through photoresist smoothing process using direct-current superposition technique [4],[5] . In this paper, we will report that photoresist smoothing work in an efficient way to pattern fidelity control in self-aligned type multiple patterning.

One of most promising technique for the extension of 193nm immersion lithography must be Self-Aligned Multiple Patterning (SAMP) at the present. We have studied this SAMP in several aspects, which are scaling capability, mitigation of process complexity, pattern fidelity, affordability and so on. On the other hand, Gridded Design Rule (GDR) concept with Single directional layout (1D layout) extended the down-scaling with 193-immersion furthermore and relieve the process variation and process complexity, represented in Optical proximity effect (OPE), by simplification of layout design. In 1D layout fabrication, Key process steps might be edge placement control on grating line and controllability of hole-shrink technique for line-cutting. This paper introduces current demonstration results on pattern transfer fidelity control and hole-shrink technique as combined with unique pattern shape repair approach.

Self-aligned multiple patterning technique has enabled the further down scaling through 193 immersion lithography extension [1-5]. In particular, focus on the logic device scaling, we have finished the verification of patterning technology of up to 10nm node [6-7], we will discuss about some patterning technologies that are required to 7nm node. For critical layers in FinFET devices that presume a 1D cell design, there is also a need not just for the scaling of grating patterns but also for pattern cutting process. In 7nm node, cutting number increase in metal or fin layer, and also pattern splitting of contact or via is complicated, so both cost reduction and process controllability including EPE are strongly required. For example, inverse hardmask scheme in metal layer can improve CD variation of the Cu wiring. Furthermore hole pattern shrink technology in contact layer, by the combination with the exposure technique which has k1 0.25 or less, can achieve both cost reduction and reducing the numbers of pitch splitting. This paper presents the possibility of immersion-based multiple patterning techniques for up to 7nm node.

Multi-patterning technology using 193nm immersion lithography has been used since the 22nm logic node generation and it appears that it will continue to be used as far as the 14nm generation. At the same time, the industry trend is to simplify pattern design and reduce complexity in lithography though single directional (1D) layout[1]. On the other hand, there is increasing concern about pattern placement error in the application of this technology. This paper focuses on pattern placement variation in the process steps of pattern formation in 1D layout design, presents the results of a study on the effects of factors other than overlay accuracy on microscopic behavior, and describes techniques for improving pattern placement.

Scaling in the manufacture of semiconductor devices has come to be supported by advances in photolithography technology. Looking to the future, we can expect even more advances in photolithography, but at present, multi-patterning using 193nm immersion lithography is finding widespread use as an alternative technology that can contribute greatly to even higher levels of integration in semiconductor devices in combination with 1D layout. However, given increasingly complicated processes and sharp jumps in cost impact with this approach, the ideal solution would be one based on the optical reduction projection method as in the past. We anticipate the appearance of EUV technology as a next-generation lithography technology that will achieve a complementary convergence with etching and film-growing techniques developed with multi-patterning technology.

The optical projection technique with evolution of Exposure wave length (λ) and Numerical Aperture (NA) has been historically driven Photolithographic scaling. Although the delay of EUV tool for HVM has been concerned, scaling is going on steadily after limitation of 193nm-immersion technique. Double patterning process has been firstly adopted in 30nm node device of memory device, and evolved step by step from SADP, SAQP to SAOP [1][2][3]. Self-Aligned Multiple-Patterning (SAMP) with 193-immersion is getting most promising technology for further downwards scaling at the present. For the extension of 193-immersion, many solutions in mask and illumination area were suggested, and these are represented by SMO (Source and Mask Optimization) and linked to “Computational lithography”. Furthermore, the change of device layout design to 1D (Single directional) layout [4] is the solution to mitigate several process issues, which are represented by process variability, pattern fidelity and Edge placement error (EPE). This paper presents the results of observing pattern fidelity in the multiple patterning process from many aspects and the results of testing a technique for high-accuracy management of pattern fidelity in 1D layout.