Select Transistor Modulated Cell Array Structure Test Application in EEPROM Process Reliability

Non-volatile memory process development time is constantly decreasing and therefore it is necessary to anticipate any useful information both for design optimisation and for reliability assessment. We describe the select transistor modulated cell array structure test (STM-CAST), based on a simple test structure consisting of a not addressable EEPROM cell array with parallel connection of all the memory transistors. The measurement methodology is very simple, too: from the transfer characteristic measured under select transistor clamping bias it is possible to obtain accurate information on the complete threshold voltage distribution of the cells in the array. The select transistor modulation allows to eliminate all the undesired resistive loads always present in the cell array structure, so that the contribution of cells with higher threshold voltage to the total measured current is measurable, and the total threshold voltage distribution is measured. We discuss in detail the structure working principle and different levels of approximation for the data analysis. The simplest estimation of the threshold voltage distribution can be obtained assuming a step-like current voltage characteristic for each EEPROM element, consequence of the select transistor clamping effect. A more accurate approximation, especially useful in case of normal threshold voltage distributions, can be obtained by a Gaussian fit of the single cell transconductance. The threshold voltage distribution is obtained by the analytical solution of the convolution integral fitting the CAST transconductance. In the general case, valid for any distribution, a numerical approach is necessary. The threshold voltage distribution can be obtained thanks to the select transistor clamping action; all its effects are discussed in detail. We present several applications of this structure and methodology in real studies at early process development, including process/design reliability evaluation, bake retention, control gate stress, programming pulse optimisation.