The effect of back-end of line (BEOL) process on cell performance and reliability of Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM) is discussed. The microscopic evolution of the Ge-rich GST alloy during process is the focus of the first part of the paper. A new metric for quantification of active material modifications is introduced to better follow its evolution with process sequence. Ge clustering has been shown to occur during the fabrication, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is identified, and an extensive electrical characterization of array performance and reliability is done on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

Embedded phase change memory (PCM) show optimized performance and reliability thanks to Ge enrichment of the active GeSbTe material. This work presents the detailed TCAD model for embedded PCMs able to physically reproduce the program operation, crystallization and its impact on reliability and the absence of thermal disturb phenomena. The model shows a good agreement with 28nm technology node structures and a comparison with conventional 225-GST used for stand-alone memory is also proposed.

One of the most promising Embedded Phase Change Memory (ePCM) integration scheme is the wall architecture, which relies on the dedicated Heater element to thermally switch the device. A good control of this element is a key factor to satisfy the performance requirements of the automotive market. In this paper, the optimization of TiSiN Heater system in $0.019\mu \mathrm{m}^{2}\text{ePCM}$ cell realized with 28nm FDSOI technology is extensively reported. Key fabrication parameters defining heating efficiency are investigated, covering a large range of Heater resistance. Their impact on $e$ PCM reliability of elementary device and 16MB memory array, considering both retention and endurance, is characterized and the key role played by Heater is demonstrated, opening a path to scaled programming currents. Finally, TiSiN ALD deposition process is proposed as the solution to improve uniformity and scalability of Heater resistance. As Heater is the variable controlling the whole system, this approach guarantees the robustness of $e$ PCM technology for automotive grade-0 applications.

Fabrication and electrical characteristics of a new BJT selector enabling a 1T1R embedded phase change material (ePCM) memory cell of 0.019µm 2 are extensively reported in this paper. A smart process, leveraging the specific feature of the FDSOI substrates with its thin buried oxide (BOX) has been developed to create an innovative isolation wall between bitlines (BL) and to totally suppress the parasitic BL-to-BL leakage. A current of 300µA at V EB =1.6V and a leakage as low as 8pA/cell at V BE =3.6V, 165°C were achieved. Compared to its MOS selector counterpart, -48% cell area reduction is obtained at same driving current, demonstrating the high density and the cost competitiveness of this FDSOI BJT selector solution. Finally, a shrunk BJT-ePCM cell of 0.015µm 2 , which is the smallest 1T1R eNVM reported to date, is demonstrated for the first time.

This paper discusses the effect of back-end of line (BEOL) process on cell performance for a Phase-Change Memory embedded in a 28nm FD-SOI platform (ePCM). The impact of BEOL is first shown by describing the microscopic evolution of the active Ge-rich GST alloy during process. Ge clustering has been proven to occur during the fabrication process, impacting the pristine resistance and the after forming cell performance. Two different BEOL processes are then benchmarked in terms of key performance. An optimized process is then identified, and an extensive electrical characterization of array performance and reliability is performed on the full 16MB chip. The optimized BEOL process results in a memory cell fully compatible with the requirements for demanding automotive applications.

In this paper we present an enhancement of our 28nm FDSOI-PCM solution using Bipolar Junction Transistor (BJT) selector co-integrated with triple gate oxide devices scheme (logic/1,8V/5V) for advanced automotive microcontroller designs. Leveraging FDSOI substrate, innovative Super-STI (SSTI) scheme has been developed enabling 0,019um 2 PCM cell. It is the densest eNVM cell reported so far, based on our knowledge. Ultimate analog performance targets for automotive have been successfully demonstrated without compromising reliability for 5V transistor thanks to a novel gate stack & spacers architecture. Automotive grade-0 reliability criteria have been achieved on 16MB PCM array, including 3x aggressive runs of soldering reflow thermal stress (265°C/210s). Finally, wide reading window has been shown even after 250K writing operation at 165°C.

Quenching-time characterization is the way to measure the speed of chalcogenide material to transform from the amorphous (RESET) state to the crystalline (SET) one after application of a proper programming pulse. It is here proposed to study the impact of process and programming conditions on cell performances, highlighting possible composition variation, and modifications of the physical dimension of the PCM active volume (the dome).

For the first time we propose a 28nm FDSOI e-NVM solution for automotive micro-controller applications using a Phase Change Memory (PCM) based on chalcogenide ternary material. A complete array organization is described exploiting body biasing capability of Fully Depleted Silicon On Insulator (FDSOI) transistors. Leveraging triple gate oxide integration with high-k metal gate (HKMG) stack, a true 5V transistor with high analog performance has been demonstrated. Reliable PCM 0,036um 2 analytical cell with 2 decades programming window after 1 Million of cycles has been demonstrated. Finally, current distributions based on a fully integrated 16MB macro-cell is presented achieving Bit Error Rate (BER) <; 10 -8 after multiple bakes at 150°C and 10k cycling of code storage memory.

Today, the most widely diffused and popular non volatile memory solutions for system on chip (SOC) are Flash and EEPROM. EEPROM is especially useful for applications not requiring a large amount of memory and strongly demanding for a very high number of W/E cycles in conjunction with capability to erase small amount of memory (word size) in a short time (few ms). On the other hand the Flash solution is more attractive for applications with higher amount of memory, not requiring erasing at word level. Focusing on the field of SIM Market (Smartcard for Telecom application), the trend today is to reduce cost while keeping almost the same amount of NVM memory, with the ROM size slightly increasing due to the introduction of new software features. This caused a price pressure and forced major SIM Suppliers in the reduction of NVM cell size. In this scenario EEPROM has been scaled down to the ultimate limit for 2T architecture, showing an evident difficulty in a further scaling down perspective. At the same time, the feature of ROM personalization is also a cost, and ROM replacement with NMV would be more than welcome. This paper illustrates a solution addressing both problems, with the adoption of a scalable Flash cell and a proper Memory Architecture integrated in 90 nm CMOS technology, first in the world for SIM applications.

Non-volatile memory process development time is constantly decreasing and therefore it is necessary to anticipate any useful information both for design optimisation and for reliability assessment. We describe the select transistor modulated cell array structure test (STM-CAST), based on a simple test structure consisting of a not addressable EEPROM cell array with parallel connection of all the memory transistors. The measurement methodology is very simple, too: from the transfer characteristic measured under select transistor clamping bias it is possible to obtain accurate information on the complete threshold voltage distribution of the cells in the array. The select transistor modulation allows to eliminate all the undesired resistive loads always present in the cell array structure, so that the contribution of cells with higher threshold voltage to the total measured current is measurable, and the total threshold voltage distribution is measured. We discuss in detail the structure working principle and different levels of approximation for the data analysis. The simplest estimation of the threshold voltage distribution can be obtained assuming a step-like current voltage characteristic for each EEPROM element, consequence of the select transistor clamping effect. A more accurate approximation, especially useful in case of normal threshold voltage distributions, can be obtained by a Gaussian fit of the single cell transconductance. The threshold voltage distribution is obtained by the analytical solution of the convolution integral fitting the CAST transconductance. In the general case, valid for any distribution, a numerical approach is necessary. The threshold voltage distribution can be obtained thanks to the select transistor clamping action; all its effects are discussed in detail. We present several applications of this structure and methodology in real studies at early process development, including process/design reliability evaluation, bake retention, control gate stress, programming pulse optimisation.

We present a simple structure and a simple test to obtain important information on EEPROM cells' reliability, such as the threshold voltage distribution of the cell array and its evolution during a bake retention experiment. Both intrinsic and extrinsic characteristics can be determined, thanks to the clamping effect of the select transistor in series to each memory transistor. The method is useful not only during the early process development stage, but also as a process monitor. (C) 2000 Elsevier Science Ltd. All rights reserved.

In this paper we show that dopant decoration of process-induced defects is responsible for a failure mechanism of memory devices. From the electrical point-of-view, the defect-related failure consists in a source-to-drain resistive path formed by junction piping. This mechanism is made active by the very close spacing which is typical of present device structures. A device-like test structure is used for defect detection. This structure proves to be a very effective tool for studying the impact of various process steps on defect generation, in that it allowes statistical data about the formation of these defects to be collected. TEM analyses are extensively used for studying the evolution of end-of-range defects during subsequent thermal treatments and for measuring the amorphous layer width under various implantation conditions. The role of high dose implantations in the generation of this sort of defects is discussed. Even if the amorphous layer is completely recovered by a suitable recristallization annealing, residual defects grow and become dopant-decorated during post-implantation thermal treatments. Defect density is increased by oxidizing treatments. In this case point defect injection is active both in enhancing dopant diffusion and in growing defects. Defect formation is suppressed if the amorphous layer is made very shallow (= 50 nm) by suitable choices of the screen oxide and of the implantation energy. A binary collision code is used in order to estimate the dependence on energy of the self-interstitial excess outside the amorphous region. The results of these calculations indicate that defect suppression can be tentatively explained by point defect annihilation at the silicon surface.

We have investigated the degradation of tunnel oxides due to Fowler–Nordheim electron injection from polysilicon gate. Tested devices are n-MOSFET normally used for Flash EPROM applications with four different technologies for the tunnel oxide layer. Stresses have been performed at different source and drain bias conditions for a total injected charge up to 1C/cm2. The oxide characteristics and degradation have been determined comparing the MOSFET threshold voltage and transconductance peak for as received devices and after each stress step.