Three-Dimensional Logic in Memory Device for Ultra-Low Power Parallel Evolutionary Computing

In this paper, a three-dimensional all-spin parallel evolutionary computing (ASPEC) device is proposed to realize the evolutionary algorithm in a single device instead of a traditional CMOS circuit. A 3D magnetic tunnel junction (MTJ) array is used to store the genetic information of the whole population. Using the spin transfer torque (STT) effect with spin diffusion mechanism, we realize a parallel computing scheme for chromosome replication, proliferation, crossover, gene mutation, and selection. Getting benefit from the logic-in-memory (LIM) architecture consisting of MTJ arrays, the ASPEC device is not only non-volatile but also avoids memory wall. Our results show that the time complexity of evolutionary algorithms is reduced due to the parallel computing design, and the energy consumption is also significantly cut down owing to non-volatility and its avoidance of Joule heating.