Amorphous oxide defects in MoS2/high-κ gate stacks cause severe reliability issues such as hysteresis and bias-temperature instabilities (BTI), hindering 2D field-effect transistors (FETs) from achieving Si-standard reliability. While existing studies primarily focus on the energetic alignment between oxide defect bands and the channel conduction band edge, the role of the van der Waals (vdW) gap as a defining feature of 2D interfaces remains underexplored. Here, by performing TCAD simulations on scaled top-gated MoS2/HfO2 FETs with border oxide traps, we reveal that the vdW gap plays a dual role in charge trapping dynamics. For deep traps, it eliminates contact-induced band bending, suppressing pre-filling and enabling faster trapping at high gate bias. For shallow traps, it introduces a tunneling barrier that slows charge trapping and suppresses emission to the gate by limiting the downward shift of the gate Fermi level, thereby increasing hysteresis. Consequently, the bias stability of nanoscale MoS2 FETs is governed not only by the energetic alignment of defect bands but also by the vdW gap as a non-negligible factor. These findings provide critical insights for the reliability-aware design of future 2D electronics with proper consideration of the vdW gap.
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