Edge computing and always-on intelligent systems impose growing demands for high-density and low-power embedded memories. Voltage-controlled magnetic anisotropy magnetic random-access memory (VCMA-MRAM) is a promising candidate due to its sub-nanosecond and energy-efficient write operation. Conventional VCMA-MRAM adopts a source-line (SL)-write scheme to suppress unselected bit-cell write disturbance, but it requires a boosted word-line (WL) voltage to ensure sufficient write margin. To address this issue, this paper proposes a bit-line (BL)-write VCMA-MRAM architecture that eliminates the need for WL voltage boosting and uses a BL standby biasing scheme to suppress write disturbance. Specifically, the BL standby bias is set to half of the write voltage, which reduces the peak parasitic pulse across unselected magnetic tunnel junctions (MTJs). Under the evaluated conditions, this voltage level does not induce unintended switching, enabling reliable BL writing while reducing the WL voltage by 33.33% compared with the conventional SL-write scheme. Furthermore, the optimized BL-write architecture reduces the bit-cell area by 41.67% owing to the simplified interconnection between MTJs and transistors and the grounded-SL layout. Additionally, the optimized BL-write architecture, together with the proposed BL standby biasing scheme, reduces the write and read energies by 61.27% and 61.00%, respectively. The proposed VCMA-MRAM design also supports reconfigurable physically unclonable function (PUF) operation through long-pulse stochastic switching without additional dedicated PUF cells, reducing the reconfiguration energy by 80.65%.
HfO2-based ferroelectric films are promising for next-generation nonvolatile memory due to their excellent CMOS compatibility. However, the severe imprint effect remains a key reliability issue of the films. In this work, a controllable WOx interlayer was introduced into W/WOx/HfZrO2/W ferroelectric capacitors by O2 plasma oxidation of the tungsten film. The effects of WOx interlayer on polarization, endurance, and imprint characteristics of the capacitor devices are systematically investigated. The optimized device exhibits an increase in 2Pr from 33 to 45 μC/cm2 and an endurance improvement to 108 cycles. Imprint measurements show that the WOx interlayer could effectively suppress the P–V loop shift, especially at high temperature, reducing the shift by 41%. The results of this study demonstrate that WOx interfacial engineering, acting as both an interfacial buffer and an oxygen reservoir, effectively improves the imprint behavior and reliability of HfO2-based ferroelectric devices.
We demonstrate an ambipolar charge-trap (CT) memory device employing Schottky barrier (SB) source/drain contacts and investigate the impact of channel width (Wc) scaling on memory characteristics. The device exhibits dual n- and p-channel operation enabled by comparable Schottky barrier heights, allowing flexible memory functionality within a single cell. Efficient hot-carrier generation is achieved at relatively low drain voltages owing to the strong electric field concentrated at the SB contacts. The device shows enhanced program performance in n-channel operation, with ~1.5 times larger threshold voltage shift compared to p-channel operation. An increase in threshold voltage shift (ΔVth) is observed with decreasing Wc for both polarities. An effective Schottky barrier height (SBH) analysis reveals that this behavior originates from Wc-dependent modulation of the effective SBH, which enhances carrier injection efficiency. These results establish a direct correlation between device geometry and SBH, providing a key design strategy for scalable and high-performance charge-trap memory devices.
Amorphous oxide defects in MoS2/high-κ gate stacks cause severe reliability issues such as hysteresis and bias-temperature instabilities (BTI), hindering 2D field-effect transistors (FETs) from achieving Si-standard reliability. While existing studies primarily focus on the energetic alignment between oxide defect bands and the channel conduction band edge, the role of the van der Waals (vdW) gap as a defining feature of 2D interfaces remains underexplored. Here, by performing TCAD simulations on scaled top-gated MoS2/HfO2 FETs with border oxide traps, we reveal that the vdW gap plays a dual role in charge trapping dynamics. For deep traps, it eliminates contact-induced band bending, suppressing pre-filling and enabling faster trapping at high gate bias. For shallow traps, it introduces a tunneling barrier that slows charge trapping and suppresses emission to the gate by limiting the downward shift of the gate Fermi level, thereby increasing hysteresis. Consequently, the bias stability of nanoscale MoS2 FETs is governed not only by the energetic alignment of defect bands but also by the vdW gap as a non-negligible factor. These findings provide critical insights for the reliability-aware design of future 2D electronics with proper consideration of the vdW gap.
Line width roughness (LWR) and hot-carrier degradation (HCD) pose critical challenges to the advancement of nanoscale complementary metal oxide semiconductor (CMOS) technology. The correlation between gate \ active area (AA) LWR and HCD-induced variability remains insufficiently explored. This work studies LWR-driven variability of HCD in CMOS devices. The experimental results show that reductions of 1.81 nm in active area LWR and 1.16 nm in gate LWR decrease hot carrier degradation variation by 18.6% and 34.7%, respectively. Moreover, mechanistic insights from combined electrical characterization and simulations, reveal that gate LWR leads to non-uniform doping and electric-field distribution in the channel, increasing local carrier temperature and interface-trap density. Whereas AA LWR modifies the potential barrier in the space-charge region near the channel boundary and enhances the local electric field and carrier concentration along the channel edge. Furthermore, by reducing both AA and gate LWR, barrier fluctuation along the junction line can be suppressed, thereby alleviating HCD-induced current-onset voltage variability. This work demonstrates that optimizing AA and gate LWR is essential for enhancing the reliability and variability of nanoscale MOSFETs and integrated circuits.
Thirty-nanometer-thick (Al0.9Sc0.1)N films were deposited on 5 nm-thick Pt bottom electrodes on 300 mm-diameter Si wafers, and the wafer-scale uniformity of the film properties was evaluated. The films exhibited a thickness uniformity of 0.6% (1σ), a surface roughness uniformity of 3.3% (1σ), and a Sc/(Al + Sc) ratio uniformity of 1.4% (1σ). The degree of crystal orientation, evaluated from the full width at half maximum (FWHM) value of the X-ray diffraction (XRD) (002) rocking curve, showed a wafer-scale uniformity of 1.3% (1σ). A 5 nm-thick Pt top electrode was deposited to form a total 40 nm-thick Pt/(Al0.9Sc0.1)N/Pt capacitor stack, which showed, as measured by positive-up-negative-down (PUND), a remanent polarization (Pr) value of >100 μC cm−2 and a coercive field (Ec) value with a wafer-scale uniformity of 1.9% (1σ) across the wafer. Retention at 85 °C showed <∼10% Pr loss up to 105 s. To assess process reproducibility, process stability over a 500-wafer run was evaluated. Wafer-to-wafer variations were 1.0% (1σ) in thickness, 2.5% (1σ) in surface roughness, 0.9% (1σ) in the Sc/(Al + Sc) ratio, 3.5% (1σ) in the FWHM value of the XRD (002) rocking curve, 3.1% (1σ) in the Pr value, and 1.0% (1σ) in the Ec value, confirming stable film quality and crystal orientation during continuous deposition over the 500-wafer run. This work presents a wafer-scale evaluation of a 40 nm-total-thickness Pt/(Al0.9Sc0.1)N/Pt capacitor stack on 300 mm-diameter Si wafers. The present results demonstrate that (Al0.9Sc0.1)N films achieve the uniformity and stability required for high-volume manufacturing, enabling process integration for logic-embedded ferroelectric memory applications.
At present, design of memristor-based chaotic systems with enhanced performance has emerged as a research focus. In this study, a CMOS memristive emulator characterized by exponential nonlinearity and pinched-hysteresis behavior under sinusoidal excitation is introduced into the Chen chaotic system as a nonlinear state-dependent element. The introduction of this memristive nonlinear element significantly increases system complexity, leading to more intricate alternating dynamical behaviors as parameters vary. This enables richer evolutionary trajectories within the parameter space and extends the range over which chaotic behavior occurs. A fully integrated chaotic circuit is designed for the proposed system using operational amplifiers and multipliers. Unlike conventional Chen chaotic circuits that rely on discrete components, the proposed circuit achieves full integration and is fabricated using the SMIC 180 nm CMOS process, occupying a compact chip area of only 0.0672 mm2. Circuit-level simulation results demonstrate that the circuit consumes merely 18.54 mW under a +/- 2.5 V supply voltage and achieves a maximum Lyapunov exponent of 1.58 based on the generated time series, confirming the chaotic behavior of the system . These simulation results indicate that the proposed design has potential advantages in terms of compact layout area, low supply voltage, and reduced power consumption. Therefore, this work provides a simulation-verified circuit design reference and a potential prototype for the further development of integrated chaotic systems for information security applications.
This manuscript presents a dual-band Voltage-Controlled Oscillator (VCO) design with temperature resistance circuit. It employs two Temperature Resistant VCOs (TRVCOs) that can operate from 350 MHz to 2.4 GHz and 2 GHz to 6.29 GHz. A temperature resistant circuit (TRC) is used to convert the temperature variation to frequency which can be used as one of the features for estimation of aging effect of the circuit using machine learning model. Three models -linear regression, polynomial regression (2nd degree) and random forest are considered and trained using synthetic data and random forest outperformed the other two in terms of mean absolute error. The variation of the frequency is controlled up to 260 MHz at 1500 °C, making it useful for use even in harsh environment. The design is implemented in cadence 90 nm gpdk CMOS Technology.
Ternary logic offers significant potential for enhancing computational capabilities due to its higher data density than conventional binary logic. However, the complexity of ternary logic gate implementation has limited its practical adoption for decades. With their unique negative differential resistance (NDR) characteristics, tunnel diodes present a promising solution for realizing ternary logic gates with a more compact structure and reduced circuit overhead. Despite this potential, research on employing tunnel diodes for ternary logic remains scarce. In this work, we optimize an empirical model for tunnel diodes to balance computational efficiency and accuracy, enabling the integration of tunnel diodes into high-precision simulations for electronic design automation (EDA) tools. We then design and implement standard ternary inverters using tunnel diodes in various configurations, achieving reduced circuit complexity compared to conventional ternary approaches. Load-line analysis and transient simulations in HSPICE are conducted to elucidate the operating mechanism and evaluate power and delay performance. This research establishes a foundation for circuit design utilizing the compact model of tunnel diodes and demonstrates the feasibility of implementing ternary logic gates using devices with NDR characteristics.
Nanoribbons of monolayer germanium-sulfide (GeSNR) are promising as channel material in future nanosheet/nanoribbon gate-all-around field-effect transistors (GAA FET). Here we study the impact of edge defects on the electronic and transport properties of GeSNRs using ab initio quantum transport calculations and performance of ballistic GeSNR GAA FETs. We show that the transport gap of GeSNRs is immune to edge defects, while electron and hole conductances deteriorate with the increasing defect density. Furthermore, we demonstrate that S vacancies have a more pronounced impact on the ON-state current than Ge vacancies, highlighting interesting nuances concerning atomic defects on the edges. Nevertheless, the resulting carrier conductances are superior to those calculated for graphene nanoribbons, making GeSNRs a plausible channel material for GAA FETs.
The increase in computational demand for applications such as artificial intelligence has now outpaced Moore's Law. Ultra-low voltage CMOS operation is urgently needed to address the everlasting energy consumption growth. In this review article, we introduce steep sub-threshold swing devices such as the tunneling FET and the negative-capacitance FET (NCFET), which allow the use of a very low supply voltage. Ferroelectric materials not only enable NCFET but can also be used for memory at cryogenic temperatures. In addition, for high-performance computing in particular, operating CMOS devices at ultra-low (cryogenic) temperatures has been shown to be an energy-efficient solution despite cooling power/facility requirements. We will review the physics and modeling of cryogenic CMOS technology for the incumbent planar UTB-SOI and FinFET devices, focusing on the limits of sub-threshold swing at very low temperature. Finally, we will briefly touch upon the role of cryogenic CMOS in quantum computation.
Conventional backside power delivery network (BSPDN) architectures for complementary field-effect transistors (CFETs) suffer from increasing parasitic penalties due to high-aspect-ratio “super-vias” at advanced nodes. Based on the recently reported Backside Gate Contact (BGC)-enabled hybrid power delivery framework (Park et al., 2024), we propose a co-optimized set of A7 monolithic CFET standard cells — ring oscillator (RO), multiplexer (MUX), and SRAM — that eliminates super-vias and balances front-side/backside routing. In particular, we propose a novel SRAM architecture in which, enabled by a Backside Spacer Merge technique, the cross-coupled interconnects are relocated to the wafer backside. Multi-level process-to-circuit simulations benchmark our cells against conventional BSPDN, BSPDN with direct backside contact (DBC), and standalone hybrid PDN. The proposed RO achieves a 12% frequency increase with 9% lower energy than the hybrid counterpart without BGC. The proposed SRAM, compared to the same hybrid-PDN-only baseline, reduces read and write latencies by 22.8% and 29.4% while maintaining superior read/write stability. The results demonstrate BGC-aware cell-level co-design as a scalable path for CFET logic and memory integration.
Copper physical vapor deposition (PVD) for high-aspect-ratio via metallization remains challenging due to limited step coverage and strong process non-uniformities induced by ionized flux control. In this work, a systematic investigation of copper PVD process parameters is conducted using an advanced self-ionized plasma reactor. The influence of DC power, AC bias power, and electromagnet current is first evaluated on blanket wafers, highlighting distinct deposition and resputtering regimes. Multistep deposition–etch recipes are then designed and optimized based on these findings. Validation on patterned wafers with 2.7µm-tall vias demonstrates that appropriate sequencing and cycling of low- and high-bias steps significantly enhance via coverage. Compared to the process of record, a fivefold improvement in copper seed conformity is achieved, increasing via coverage from 4.8% to 27.7% while maintaining acceptable field uniformity. These results emphasize the critical role of recipe architecture in extending PVD applicability to aggressive aspect-ratio interconnects.
As a representative two-dimensional (2D) material, graphene is promising for next-generation electronics with high carrier mobility. In order to reduce the interface scattering, however, graphene devices often require an atomically flat, chemically inert, ultrathin and high-x gate dielectric. Conventional dielectric layers suffer from surface roughness, whereas ultrathin high-x films are prone to pinhole-induced leakage. Here, we report the liquid-phase-exfoliated 2D perovskite oxide bismuth titanate (Bi4Ti3O12, BTO) nanosheet film with a high dielectric constant of 22.5. Using a van der Waals (vdW) transfer, the BTO film is integrated as a top-gate dielectric to construct the dual-gate BTO/graphene transistors. The top-gate capacitance of the device was estimated to be 903 nF/cm2. Owing to the reduced interfacial scattering, the graphene transistors operate below 1 V at room temperature and exhibit a high carrier mobility of 2840 cm2V-1 s-1, while maintaining a small leakage current density of only 0.012 pA/mu m2. The present 2D devices highlight the critical role and the unique advantages of high-x BTO dielectrics.
Conventional memristive devices mainly rely on external current compliance modulation or materials engineering to switch between volatile and non-volatile modes, resulting in higher circuit complexity. Here, we introduce a geometry-driven strategy that intrinsically modulates resistive switching behavior without external current compliance control. Using grayscale thermal probe lithography, we fabricated 3D nanocone-structured Ag electrodes with precisely controlled depths on the silk fibroin (SF) dielectric layer and constructed Au/SF/Ag-based memristors with well-defined geometries. Under an identical constant compliance current, purely geometric variation from shallow to deep nanocones induces a deterministic transition from volatile threshold switching to non-volatile bipolar memristive behavior. Simulations of the electric field and analysis of the underlying mechanism were performed. Electrical measurements verified that both volatile and non-volatile devices exhibit stable switching characteristics, as well as representative neuromorphic functions, including paired-pulse facilitation (PPF) and long-term potentiation/depression (LTP/LTD). In addition, the proposed 1S1R architecture demonstrates improved addressing performance and a similar to 100-fold reduction in static power consumption in large arrays (N = 512), offering a potential pathway for efficient and heterogeneous neuromorphic integration on a single chip.
In the nanometer regime, lithography hotspot detection is a vital step in the integrated circuit (IC) design flow to mitigate manufacturing risks and enhance yield. However, practical deployment is often hindered by severe data imbalance, excessive computational costs from high-dimensional layout data, and the limited adaptability of conventional models across varying spatial scales. To bridge these gaps, this paper proposes AdaScale-HDNet, an adaptive framework that integrates frequency-domain feature compression with dynamic multi-scale convolution and attention-guided feature fusion. By leveraging an asymptotic feature pyramid structure and optimized loss functions, the model effectively captures fine-grained geometric details while maintaining high computational efficiency. Experimental results on the ICCAD-2012 and ICCAD-2019 benchmarks demonstrate that AdaScale-HDNet achieves a superior average accuracy of 98.0% alongside a remarkably constrained false alarm count (e.g., averaging 636 on ICCAD-2012), outperforming state-of-the-art methods in both detection robustness and scalability for advanced Design-for-Manufacturing (DFM) flows.
Two-dimensional (2D) materials continue to garner significant interest for their potential in next-generation nanoelectronic devices due to their tunable electronic properties. In this context, monolayer scandium oxychloride (ScOCl) is introduced as a promising yet unexplored 2D semiconductor. Using first-principles density functional theory (DFT) calculations with the hybrid functional HSE06, we systematically investigate the impact of point defects - including oxygen vacancies, substitutional atoms (oni and on), and displacement defects - on the structural and electronic properties of ScOCl in 2 & times; 2 & times; 1 and 3 & times; 3 & times; 1 supercells. Phonon dispersion and ab initio molecular dynamics (AIMD) simulations confirm the dynamical and thermal stability of all defective configurations. Defect formation energy calculations reveal that Ni substitution (O-Ni) has the lowest formation energy of 3.00 eV, making it the most thermodynamically favorable defect. Nitrogen substitution (O-N) exhibits formation energies of 4.00 eV in the 2 & times; 2 & times; 1 supercell and 3.50 eV in the 3 & times; 3 & times; 1 supercell, indicating concentration-dependent stability. Oxygen vacancies show formation energies of 4.30 eV and 4.29 eV, respectively, while displacement defects have the highest formation energies of 5.50 eV and 5.00 eV, requiring external stimuli such as electron irradiation to form. Oxygen vacancies induce a substantial band gap reduction from 5.50 eV to 2.03-3.15 eV, while substitutional defects modulate the band gap over a wide range (3.50-5.64 eV) depending on defect concentration. Furthermore, biaxial strain provides additional tunability, with compressive strain collapsing the band gap to as low as 1.61 eV at-25%. These findings offer valuable insights into defect and strain engineering strategies for optimizing the electronic performance of ScOCl in 2D device applications.
