An optimized instruction-set encoding can reduce the silicon area and power consumption of a processor architecture implementation. However, the design space of the input encoding problem is of factorial growth with the number of instruction patterns, so effective heuristics and an automated exploration tool are required to facilitate instruction-set encoding optimization in a processor design flow. This paper proposes a novel approach based on genetic algorithms to automatically optimize the instruction-set encoding of a specific processor architecture, reducing the silicon area and power consumption requirements for specific applications and hardware implementation technologies. Furthermore, an open-source tool, called VANAGA, is presented, which implements the proposed approach and allows flexible adaptation to custom instruction-set optimization scenarios. The tool flow is evaluated with an exemplary 65 nm standard cell ASIC implementation of a minimal controller architecture with 4-bit wide opcodes (NanoController). For different optimization scenarios, logic silicon area and total power consumption vary within a design space range of 6.3% and 0.46% for different instruction-set encodings, respectively.
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