Compliance testing is mandatory when implementing the hardware architecture of a specific instruction set. The official compliance test suite with handwritten test cases for RISC-V can be helpful for this task. However, a high-quality test suite requires significant manual effort and cannot easily adapt to specific processor hardware architecture organization implementation aspects such as single-cycle, multi-cycle, or pipeline (with a different number of pipeline stages) configurations, or include an additional co-processor. This paper uses the PATARA framework, based on the REVERSI approach, to generate randomized, self-testing test cases for any RISC-V hardware implementation. The REVERSI method verifies the functionality within the same test program without requiring a golden reference model (e.g., simulator) and speeds up post-silicon validation times. With extensions to cover all possible hardware architecture implementation hazards and cache misses, a 6 pipeline-stages RV32IM hardware architecture implementation is verified functionally, reaching up to 100

With shrinking structure sizes, radiation-induced faults in microelectronic components are a concern for the design of high-reliability systems. As radiation testing is expensive, non-reproducible, and only possible after a chip has been fabricated, tools for analyzing the effect of faults on ASIC designs during the design phase are needed. FPGA-based fault-injection analysis can provide a speed-up compared to simulation, enabling higher fault-space coverage. This work presents OpenFI4ASIC, a modular open-source framework for performing fault-injection campaigns on layout netlists of ASIC designs. Faults are injected by replacing standard-cell instances with instrumented instances connected via a scan chain. This instrumentation is performed automatically by the OpenFI4ASIC framework, which also provides the hardware interfaces and software drivers to facilitate fault-emulation campaigns on an SoC FPGA. As a case study, a configurable open-source RISC-V core is evaluated for five implementations, from single-cycle to five-stage pipelined, using three standard benchmarks (ISQRT, BUBBLESORT, and CRC32). The cores are synthesized for 45nm NanGate technology, and the resulting netlists are used as input for OpenFI4ASIC and emulated on a Zynq-7000 SoC FPGA. The generated FPGA projects enable fault-injection campaigns at up to 6878.76 fault-injection runs per second, allowing full coverage of the single-bit fault within minutes. The results highlight the importance of considering the architecture implementation, showing differences of up to 30.3

To ensure the reliable operation of Field-Programmable Gate Arrays (FPGA) in radiation-affected use cases, characterizing radiation effects is of great interest. This paper extends our previous neutron irradiation experiments and characterization methodology on SRAM-based FPGAs, focusing on Single Event Transients (SET). Using the same hardware setup previously employed for Single Event Upset (SEU) characterization, multiple Artix-7-35T devices are exposed in parallel to 2.45 MeV neutron radiation. Two dedicated detection circuits, one based on latches as detector cells and one using sequential logic, are used to trace the occurrence of SETs. The results are obtained via the device readback mechanism, thereby facilitating the experimental setup by eliminating the need for external detection hardware. The presented methodology and measurements are used to derive fault models for SET, supporting the evaluation of mitigation techniques and the assessment of the error probabilities of implemented circuits. The results show that compared to SEU, SETs have a minor effect in the 28-nm technology tested under neutron irradiation.

Optimizing hardware costs and memory footprint represents a critical challenge in frequency-modulated continuous wave (FMCW) chirp radar systems for advanced driverassistance systems and autonomous driving applications. Conventional approaches to reduce sampling rates of analog-to-digital converters lead to a deterioration of key performance indicators, such as maximal range and range resolution. To overcome these limitations, a novel FMCW modulation scheme is proposed, which involves dividing the chirp sequence into blocks with dynamically increasing bandwidths, so that the lowest bandwidth ensures the required maximal range, while the highest provides the required range resolution. To avoid data loss, the antialiasing filter cutoff frequency is dynamically increased, allowing aliasing, a phenomenon traditionally considered detrimental. This approach generates ambiguities, which are then effectively resolved through a decision tree methodology. Simulation results demonstrate the benefits of the proposed scheme: it achieves range resolution comparable to high-performance modulations while maintaining the low memory footprint of memory-efficient systems. A hardware proof-of-concept test, utilizing a radar prototype and a radar target generator, validates these core principles.

In many FPGA-based systems, only sequential system control structures modeled by finite state machines are actually required. In order to deal with complexity, design time, and verification issues, which are weaknesses of traditional hardware description languages, it may be preferred to describe the control flow behaviorally in software. However, it is reported that high-level synthesis for FPGA often generates inferior results in terms of resources and performance when translating software-style control flow description to hardware. In this paper, the NanoSoftController is proposed as an open-source soft processor, which is optimized for minimal and efficient logic resource usage on FPGA platforms. It is targeted at processing sequential finite state machine functionality in software, featuring a compact ISA for control flow in embedded systems and a tiny accumulator-based data path. Furthermore, an efficient mapping of memory to small distributed LUT RAM instances enables its use as a system state machine controller in even very resource-constrained FPGA designs, requiring only 104 slice LUTs and 76 slice registers in total. However, despite all optimizations, in a case study with high-level synthesis results of three reference software-style control applications, i.e., electronic door lock, smart glucose sensor, and sequential sensor network node, a better resource efficiency could not be shown. We evaluate the negative results and provide lessons we learned from them.

This work presents a physically based simulation evaluation of the effects of single ionizing particles and displacement damage on logic inverter gates in a complementary metal-oxide semiconductor (CMOS) with 180 nm structure size. A technology computer-aided-design (TCAD) model is combined with a radiation model to allow the simulation of charged particles with a linear energy transfer (LET) between 1 and 100 MeV center dot cm(2)/mg. For displacement damage simulation, proton energies between 1 and 10 MeV and neutron energies between 1.6 and 14 MeV have been evaluated to estimate the resulting transistor threshold voltages.

The growth of artificial intelligence (AI) applications has increased the demand for high-performance computing and highlighted the critical bottleneck caused by slower advances in memory technologies compared to those in computing. This paper presents a comprehensive approach to address memory performance challenges by integrating High Bandwidth Memory (HBM) with a novel multi-port Direct Cached Memory Access (DCMA) architecture that efficiently leverages the HBM’s band-width by implementing a complex parallel cache mechanism to exploit the inherent spatial and temporal data locality of the running application. However, harnessing the proposed DCMA’s full potential depends on the application, demanding sophisticated strategies for optimal data flow and memory access management. Therefore, the complexity of exploring the vast parameter space of such memory architectures is addressed by employing an FPGA emulation-based rapid prototyping framework, specifically TAPRE-HBM, which provides a more accurate representation of memory behavior through direct trace processing on hardware. Our contributions include the detailed architecture of the proposed HBM-optimized, multi-port DCMA system, its integration with a massive-parallel vector processor, and initial performance evaluations using the TAPRE-HBM framework on a Xilinx Alveo U55C FPGA card. Preliminary results show the importance of performing a design space exploration to choose the optimal architecture configuration for a target application to handle memory-intensive tasks. The optimal choice can improve the performance up to 32.8% for the same vector processor and HBM2 memory configuration.

Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for indexed addressing of data in memory. In vertical vector processors, different data is processed sequentially in parallel lanes and can be exchanged via chaining. This paper proposes an extension of such chaining mechanisms in a vertical vector processor architecture (V2PRO) to flexibly chain not only data but also address offsets between vector lanes. The indirect addressing enables vector access patterns with irregular strides for both register file and memory. The extension has a low hardware overhead of +4.8

State-of-the-art applications, such as convolutional neural networks, demand specialized hardware accelerators that address performance and efficiency constraints. An efficient memory hierarchy is mandatory for such hardware systems. While the memory architectures of general-purpose processors (e.g., CPU or GPUs) are based on cache systems, dedicated accelerators have mostly adopted the DMA (Direct Memory Access) concept due to the application field of image processing. DMA features like 2D data transfers or data padding can optimize the memory accesses of image processing. However, DMA lacks the capability to exploit temporal and spatial data reuse, a feature common in cache systems, particularly when multiple DMAs operate in parallel. This article proposes a novel Direct Cached Memory Access (DCMA) architecture, combining both DMA and cache methodologies and their respective advantages. Optimized for image-based AI algorithms, the DCMA architecture facilitates enhanced memory access by integrating multiple, parallel DMA ports with caching capabilities. This design allows for efficient data reuse and parallel memory access. Optimal parameters for the DCMA are determined through a comprehensive design space exploration. The DCMA is evaluated on a state-of-the-art Xilinx UltraScale+ FPGA board coupled with a massive-parallel vertical vector co-processor, called V2PRO. The results show the mitigation of the vector processor's memory bottleneck. By using the proposed DCMA, speedups of up to x17 for the ResNet-50 CNN can be achieved.

Modern embedded systems must be designed carefully to cope with the complexity and real-time requirements of modern AI (Artificial Intelligence) driven automotive applications, such as Advanced Driver-Assistance Systems (ADAS). Despite increasing complexity, the time to market is decreasing. In this work, a SystemC-based Virtual Prototype of a neural network processing platform is exploited to bypass the limitations of standalone instruction set simulators (ISS) and FPGA prototyping. The processing platform under test is based on a novel massive parallel vector processor architecture coupled with a RISC- V control core that runs widely used convolutional neural networks (CNNs) for object detection. The paper discusses the variations and appropriateness of the three prototyping methods outlined, demonstrating how the Virtual Prototype can address the aforementioned constraints, resulting in a 2.07x increase in accuracy, 16x greater configurations, and more profound insights into the system compared to standalone and FPGA prototyping.

The realization of autonomous, wearable, and implantable Systems-on-Chip (SoC) for health monitoring applications poses several challenges, such as achieving ultra-low size, cost, and power consumption, yet offering sufficient flexibility to re-program and adapt the autonomously operating SoC during the course of treatment. Commonly, programmability is not considered for ultra-low-power biomedical SoCs, since a dedicated finite state machine fixes the operation sequence. This work proposes a combination of a programmable NanoController with a SAR ADC, for potential use in ultra-low-power wearable or implantable biomedical SoCs, and integrates it as a prototype chip in a 22nm FDSOI-CMOS technology. The proposed NanoController achieves an extremely low power consumption of 505nW when programmed for 10-bit SAR ADC control and a sample rate of 100 kSamples/s. This result shows that energy efficiency and programmability during operation are not mutually exclusive for smart ultra-low-power biomedical platform chips. Based on the results of this prototype chip, a fully-integrated glucose sensor chip has been designed and submitted for fabrication, which will be evaluated in future work.

Code generation (for VLIW processor architectures) consists of instruction scheduling and register allocation. For instruction scheduling, a list scheduling heuristic is often used. However, list scheduling heuristics do not consider registerfile constraints, such as register-pressure. Thus, if the number of alive variables (i.e., virtual registers) is higher than that of available physical registers (i.e., register-pressure), register spilling instructions (i.e., store and load instructions) must be introduced to free up physical registers during register allocation. This leads to a reduction of the code compaction, decreasing the performance. This paper introduces a Graph Neural Network (GNN), that prevents register spilling by reducing the registerpressure during the instruction scheduling, and the required Reinforcement Learning (RL) environment for training. Across a test-suite including 118 random assembly programs, where 22 (18.6%) cannot schedule using list scheduling heuristic without using register spilling to alleviate register-pressure, the proposed GNN approach is able to schedule 117 programs, reducing the number of not schedulable programs to 0.8%. Moreover, the proposed GNN scheduler is able to optimally schedule up to 115 (97.5%) of the assembly programs, compared to an evolutionarybased combined instruction scheduling and register allocation approach.

The efficiency of VLIW processors can be improved by reducing the energy consumption associated with accessing the register-file. This paper presents an energy-aware register allocation approach to reduce the dynamic energy consumption of a scheduled program by using an evolutionary algorithm approach and a register access transition energy model. Additionally, the influence of instruction scheduling on energy-aware register allocation is analyzed. By using the proposed energy-aware compiler backend on synthetic applications with random data in the register-file, the dynamic energy consumption of the total processor core for an exemplary VLIW processor can be reduced by up to 21% compared to a heuristic register allocation. In real-world applications from the domain of hearing aids, energy consumption can be reduced by up to 42.7% for single applications, and 17.6% average across a range of applications.

The simulation tool GEANT4 is used for the simulation of particle interaction under radiation exposure. In this investigation the tool is used to calculate the interaction of neutrons in the SRAM cells in the active means transistor region of the cells. The goal is to determine the sensitivity to bit flips. The determination of the linear energy transfer (LET) depending on the count of transistors and cell size was investigated. The investigated SRAM-cells were fabricated in a 180nm node. The neutron radiation energy which may lead to a single event upset (SEU) was determined. The simulation was carried out with different particle energies of 1.6MeV, 2.45MeV, 6MeV and 14MeV. Threshold energies are necessary to initiate a bit flip. With the help of the simulation, the energy transfer into the active region can be determined. As a result, the adaptation of measurement (radiation time and dose) can be done.

When using Field-Programmable Gate Arrays (FPGA) in safety-critical and harsh environments, it is important to understand possible faults and implement appropriate mitigation to prevent critical system errors. Electronic components can be affected by radiation, including naturally occurring background radiation. Due to their reconfigurability, FPGAs exhibit faults not only with regard to application data but also the configuration memory, which defines the functionality of the logic circuit. This paper proposes an experiment that irradiates a logic circuit running on Artix-7-35T FPGA devices using neutron radiation with a particle energy of 2.45 MeV. During the irradiation, data is written into the on-device block RAM components and read back for further investigation. The data read back from the device is checked for errors in both the configuration and the functional level memory. A static analysis of the radiation effects, which can be used as a basis for a statistical fault model, is presented, and a brief discussion of dynamic effects, including transient errors, is given.

Modern and future AI-based automotive applications, such as autonomous driving, require the efficient real-time processing of huge amounts of data from different sensors, like camera, radar, and LiDAR. In the ZuSE-KI-AVF project, multiple university, and industry partners collaborate to develop a novel massive parallel processor architecture, based on a cus-tomized RISC-V host processor, and an efficient high-performance vertical vector coprocessor. In addition, a software development framework is also provided to efficiently program AI-based sensor processing applications. The proposed processor system was verified and evaluated on a state-of-the-art UltraScale+ FPGA board, reaching a processing performance of up to 126.9 FPS, while executing the YOLO-LITE CNN on 224x224 input images. Further optimizations of the FPGA design and the realization of the processor system on a 22nm FDSOI CMOS technology are planned.

The purpose of this research topic is to investigate the properties of reconfigurable devices (i.e., FPGA) under a radiation environment to finally propose a new methodology to design and evaluate cost-effective radiation hardening measures for reconfigurable devices. As a first step, the radiation hardness of an existing common off-the-shelf reconfigurable hardware device (FPGA) is investigated with regard to different radiation sources, including fast neutron radiation and gamma radiation. Therefore, an experiment is proposed to evaluate in run-time the changes on the memory configuration logic (e.g., configuration of each LUT, routing switches, connection boxes, DSPs, ...) and memory user logic (e.g., content of each Block RAM, Flip-Flop, Distributed RAM implemented on LUTs, ...). As a result, the chosen FPGA will be modelled in terms of fault probability of each FPGA component for a given radiation environment. These models will be integrated in a new simulation fault injection environment. In a third step, new cost-effective radiation hardening mechanisms, including configuration adjustments, design redundancy, and specialized hardware designs with error detection and correction, will be proposed and evaluated using the previously proposed environment. The proposed radiation hardening mechanisms shall be verified by using real-world radiation sources. The goal is to provide a new methodology for the design of radiation tolerant hardware architecture for FPGA devices.

Bit errors due to radiation effects are becoming increasingly important as the fabrication technologies are shrinking with every generation of integrated circuits. The resulting smaller transistors are more prone to high-energy irradiation. This is relevant in avionics or even automotive, where the safety of millions of cars must be ensured. This paper proposes an experiment, where multiple FPGAs (Field Programmable Gate Arrays) are exposed to 2.45MeV neutron irradiation in parallel. Bitflips in different memory components (Block RAM, Flip-Flops, lookup-tables and configuration memory) are detected. The results show that bitflips could be detected in every memory component in every part of the FPGA. Finally, a soft-error probability model depending on the irradiation fluence can be determined. With the probability model, future implementations of fault-tolerant hardware architectures can be tested with hardware simulations using artificially generated bitflips.