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    一种单管蓝光半导体激光器外腔装置

    KR09072794C
    发明人
    TANG XIAHUI, FANG XING, CHANG YUNWEI, DING ZEYU, CHEN GUONING, HAN JINLONG, NIU ZENGQIANG
    受让人
    UNITED WINNERS LASER CO. LTD.
    申请人
    AIRBUS FRANCE
    申请号
    084602
    申请日
    1992-12-27
    公开(公告)号
    KR09072794C
    公开(公告)日
    1993-07-20
    IPC分类号
    A01K073/04
    CPC分类号
    -
    优先权号
    121377
    123314
    优先权日
    1984-06-11
    1984-06-14
    摘要

    Body (1) has cover (15), shaft (3), and alternating stators (2) and rotors (4), each of which has holes. Body and shaft are fitted with bushes (6,7) interacting respectively with stators and rotors via ball-shaped keys (12); stators/rotors can also move axially. Cover (15) has springy element (14) to apply pressure to stators/rotors.

    Product enters via pipe (16) into radial holes (5) of stators and rotors (2,4) arriving in the channel (17) and leaving via the tangential pipe (18). Particles in the incoming flow are ground up as a result of the shear between the holes of the fixed stators and rotating rotors. The intervening gap narrows down to zero because of the resilient properties of the elements. The mechanical activation of the particles is also brought about by intense eddying, cavitation, and pulsation of flow, etc.

    USE/ADVANTAGE -In the technique of mechanical activation, and dry and wet grinding of different materials, in the chemical, ore-mining, etc. industries. Quality of the treated materials is improved. Bul.35/23.9.87

    权利要求
    1 . A nonvolatile memory device, comprising: substrate; a plurality of memory cell groups arranged in rows and columns on the substrate, each memory cell group including a plurality of memory cells stacked along a vertical direction to the substate; a plurality of bit lines; a read and write circuit connected to the columns of the plurality of memory cell groups through the plurality of bit lines respectively; and a plurality of word lines connected to the plurality of memory cells of each memory cell group, respectively; a wordline driver connected to the rows of the plurality of memory cell groups through the plurality of word lines, the word line driver being configured, during a read operation, to apply a select read voltage to a selected word line among the plurality of word lines and to apply unselected read voltages to unselected word lines among the plurality of word lines, the wordline driver being configured, during the read operation, to apply a first unselect read voltage to a first unselected word line among the plurality of word lines and to apply a second unselect read voltage a second unselected word line among the plurality of word lines, the second unselect read voltage being lower than the first unselect read voltage, and the second unselected word line being closer to the substrate than the first unselected word line.
    2 . The nonvolatile memory device of claim 1 , wherein the plurality of word lines are divided into wordline groups, each wordline group includes at least two of the plurality of word lines, the wordline driver is configured to apply different unselect read voltages to the plurality of word lines in different wordline groups, and the wordline driver to configured to apply a same unselect read voltage to the plurality of wordlines in a same wordline group.
    3 . The nonvolatile memory device of claim 1 , wherein each of the plurality of memory cell groups further includes a plurality of second memory cells stacked along the vertical direction to the substrate on the plurality of memory cells, the wordline driver is connected to the plurality of second memory cells through a plurality of second word lines, the wordline driver is configured to, during the read operation, apply a third unselect read voltage to a third unselected word line, the third unselected word line is farthest from the substrate among the plurality of word lines, the wordline driver is configured to, during the read operation, apply a fourth unselect read voltage to a fourth unselected word line, the fourth unselected word line is closest to the substrate among the plurality of second word lines, and the fourth unselect read voltage is lower than the third unselect read voltage.
    4 . The nonvolatile memory device of claim 1 , wherein each of the plurality of memory cell groups further includes a plurality of second memory cells stacked along the vertical direction to the substrate on the plurality of memory cells, the wordline driver is connected to the plurality of second memory cells through a plurality of second word lines, the wordline driver is configured to, during the read operation, apply a third unselect read voltage to a third unselected word line among the plurality of second word lines, the wordline driver is configured to, during the read operation, apply a fourth unselect read voltage to a fourth unselected word line among the plurality of second word lines, the fourth unselect read voltage is lower than the third unselect read voltage, and the fourth unselected word line is closer to the substrate than the third unselected word line.
    5 . A nonvolatile memory device comprising: a substrate; a plurality of memory cell groups arranged in rows and columns on a substrate, each memory cell group including a plurality of memory cells stacked along a vertical direction to the substrate; a plurality of bit lines; a read and write circuit connected to columns of the plurality of memory cell groups through the plurality of bit lines respectively; a plurality of wordlines connected to the plurality of memory cells of each memory cell group, respectively; a wordline driver connected to the rows of the plurality of memory cell groups through the plurality of word lines, the wordline driver being configured, during an erase operation, to apply wordline erase voltages to the plurality of word lines, the word line driver being configured, during the erase operation, to apply a first wordline erase voltage to a first word line among the plurality of word lines and to apply a second wordline erase voltage to a second word line among the plurality of wordlines, the second wordline erase voltage being higher than the first word line erase voltage, the second wordline being closer to the substrate than the first word line.
    6 . The nonvolatile memory device of claim 5 , wherein the plurality of word lines are divided into wordline groups, each wordline group includes at least two of the plurality of word lines, the wordline driver is configured to apply different wordline erase voltages to the plurality of wordlines in different wordline groups, and the word line driver is configured to apply a same wordline erase voltage to the plurality of wordlines in a same wordline group.
    7 . The nonvolatile memory device of claim 5 , wherein each of the plurality of memory cell groups further includes a plurality of second memory cells stacked along the vertical direction to the substrate on the plurality of memory cells, the wordline driver is connected to the plurality of second memory cells through a plurality of second word lines, the wordline driver is configured to, during the erase operation, apply a third wordline erase voltage to a third word line, the third unselected word line is farthest from the substrate among the plurality of word lines, the wordline driver is configured to, during the erase operation, apply a fourth wordline erase voltage to a fourth word line, the fourth word line is closest to the substrate among the plurality of second word lines, and the fourth wordline erase voltage is higher than the third wordline erase voltage.
    8 . The nonvolatile memory device of claim 5 , wherein each of the plurality of memory cell groups further includes a plurality of second memory cells stacked along the vertical direction to the substrate on the plurality of memory cells, the wordline driver is connected to the plurality of second memory cells through a plurality of second word lines, the wordline driver is configured to, during the erase operation, apply a third wordline erase voltage to a third word line among the plurality of second word lines, the wordline driver is configured to, during the erase operation, apply a fourth wordline erase voltage to a fourth word line among the plurality of second word lines, the fourth wordline erase voltage is higher than the third wordline erase voltage, and the fourth wordline is closer to the substrate than the third word line.
    9 . A nonvolatile memory device comprising: a substrate; a plurality of memory cell groups arranged in rows and columns on the substrate, each memory cell group including a plurality of memory cells stacked along a vertical direction to the substrate; a plurality of bit lines; a read and write circuit connected to the columns of the plurality of memory cell groups through the plurality of bit lines respectively; a plurality of word lines connected to the plurality of memory cells of each memory cell group, respectively; a wordline driver connected to the rows of the plurality of memory cell groups through the plurality of word lines, the wordline driver being configured, during a verify operation, to apply a select voltage to a selected word line among the plurality of word lines and to apply unselect voltages to unselected word lines among the plurality of word lines, depending on a location of a word line among the plurality of word lines, the select voltage applied to the word line being different, and depending on the location of the word line among the plurality of word lines, one of the unselect voltages applied to the word line being different.
    10 . The nonvolatile memory device of claim 9 , wherein the select voltage being lower than the unselect voltages.
    11 . The nonvolatile memory device of claim 9 , wherein the unselect voltages being different each other depending on locations of the unselected word lines.
    12 . The nonvolatile memory device of claim 9 , wherein the plurality of word lines are divided into wordline groups, each wordline group includes at least two of the plurality of word lines, the wordline driver is configured to apply different unselect voltages among the unselect voltages to the plurality of wordlines in different wordline groups, and the wordline driver to configured to apply a same unselect voltage among the unselect voltages to the plurality of word lines in a same wordline group.
    13 . The nonvolatile memory device of claim 9 , wherein the word line driver is configured, during verify operations, to apply, a first select voltage to a first word line among the plurality of word lines, and the word line driver is configured, during the verify operations, to apply, a second select voltage to a second word line among the plurality of word lines.
    14 . The nonvolatile memory device of claim 13 , wherein the first word line is closer to the substrate than the second word line, and the first select voltage is lower than the second select voltage.
    15 . The nonvolatile memory device of claim 13 , the first select voltage and the second select voltage is applied during different first and second verify operations respectively.
    16 . The nonvolatile memory device of claim 9 , wherein each of the plurality of memory cell groups further includes a plurality of second memory cells stacked along the vertical direction to the substrate on the plurality of memory cells, the wordline driver is connected to the plurality of second memory cells through a plurality of second word lines, the wordline driver is configured to, during the verify operation, apply a first unselect voltage to a first unselected word line, the first unselected word line is farthest from the substrate among the plurality of word lines, the wordline driver is configured to, during the verify operation, apply a second unselect voltage to a second unselected word line, the second unselected word line is closest to the substrate among the plurality of second word lines, and the second voltage is lower than the first voltage.
    17 . The nonvolatile memory device of claim 9 , wherein each of the plurality of memory cell groups further includes a plurality of second memory cells stacked along the vertical direction to the substrate on the plurality of memory cells, the wordline driver is connected to the plurality of second memory cells through a plurality of second word lines, the wordline driver is configured to, during a first verify operation, apply a first select voltage to a first word line among the plurality of second word lines, the wordline driver is configured to, during a second verify operation, apply a second select voltage to a second word line among the plurality of second word lines, the second select voltage is lower than the first select voltage, and the second word line is closer to the substrate than the first word line.
    18 . The nonvolatile memory device of claim 9 , wherein the wordline driver is configured to, during a first verify operation, apply a first select voltage to a first word line among the plurality of word lines, the wordline driver is configured to, during a second verify operation, apply a second select voltage to a second word line among the plurality of word lines, the second select voltage is lower than the first select voltage, and the second word line is closer to the substrate than the first word line.
    19 . The nonvolatile memory device of claim 9 , wherein the plurality of word lines are divided into wordline groups, each wordline group includes at least two of the plurality of word lines, the wordline driver is configured to apply different select voltages to each of the plurality of word lines in different wordline groups, and the wordline driver to configured to apply a same select voltage to each of the plurality of wordlines in a same wordline group.
    20 . The nonvolatile memory device of claim 19 , wherein the different select voltages or the same select voltage is applied during different first and second verify operations respectively.
    说明书
    [0001]FIELD OF INVENTION
    [0002]The present invention relates generally to design and validation methods and techniques applicable to designing complex electronic circuits. In particular, the present invention relates to a methodology for verifying and validating electronic circuit designs that are particularly applicable to system-on-a-chip and ultra large scale integrated circuit type electronic circuits.
    [0003]BACKGROUND OF THE INVENTION
    [0004]As the level of integration continues to advance, many complex electronic logic systems can now be implemented on a single integrated circuit (IC). Such an IC, often known as “system on a chip (SoC)” or “ultra large scale integrated circuit (ULSI)” in the art, includes multiple complex components (e.g., micro-processor, digital signal processor, peripheral and memory controllers), many of which may be individually obtained as “off-the-shelf” electronic circuit designs from numerous vendors in the market. These electronic circuit designs are known as “IPs 1 ” to those skilled in the art. 1 The term “IP” stands for “intellectual property.” Designers of these electronic circuits provide the designs to their customers in the form of data files which are readable by popular electronic design automation (EDA) tools. The customers of these designers then integrate these “IPs” into their own circuit designs. As an IP vendor does not provide a manufactured article here—the electronic deign is typically provided as design data represented in electronic form (e.g., stored in a storage medium, such as a compact disk, or as a stream of bits downloaded from a server via the Internet)—it has become customary in the art to refer to such electronic circuit design products as “IPs”.
    [0005]In U.S. Pat. No. 6,701,491, entitled “Input/output probing apparatus and input/output probing method using the same, and mixed emulation/simulation method based on it” by Yang, an interactive environment is disclosed for IC designers to conduct emulation sessions back and forth between a hardware accelerator and a software simulator. Correspondingly, memory states and logic storage node states are swapped between the accelerator and the simulator. A complete context switch is performed to create a time-shared environment on the hardware accelerator, so that the hardware accelerator can be shared among multiple IC designers. In general, in a similar manner, multiple accelerators can be interconnected with multiple simulators and multiple workstations to allow multiple designers to do interactive operations and to shift back and forth between hardware emulation and software simulation.
    [0006]A mixed emulation and simulation method is also disclosed by Yang. Here, input/output hardware probing is performed by emulation for verification. At least one semiconductor chip is used which implements an extended design verification target circuit by adding an IOP-probing supplementary circuit to the design verification target circuit. The IOP-probing supplementary circuit includes an input/output probing interface module. In this system, an input/output probing system controller generates the IOP-probing supplementary circuit for the design verification target circuit. The design verification target circuit is implemented in one or more semiconductor chips mounted on a prototyping board or specified by a hardware description language (HDL) code—which indicates the behavior of the IOP-probing supplementary circuit—for simulation on a simulator. Emulation and simulation are then performed in turn for one or more times, as necessary, by exchanging state information in an automated manner between a suitable prototyping board and a suitable simulator. Furthermore, the state information is completely exchanged in an automated manner between the prototyping board and the simulator by the IOP-probing supplementary circuit-based input/output probing. With the IOP-probing supplementary circuit, another mixed emulation/simulation process is also disclosed whose operating mode is conditionally based upon a pre-determined switching condition queue on a time order, switched between simulation and emulation during the process until the operating mode switching queue becomes empty.
    [0007]In U.S. Pat. No. 6,389,379 entitled “Converification system and method” by Lin, et al, a coverification system and an associated method are disclosed. The coverification system includes a reconfigurable computing system and a reconfigurable computing hardware array. The reconfigurable computing system contains a CPU and memory for processing data for modeling the entire user design in software. In some instances, a target system and external I/O devices are not necessary, as they can be modeled in software. In other instances, the target system and external I/O devices are coupled to the coverification system to achieve speed and to allow use of actual data, rather than simulated test bench data.
    [0008]The disclosed coverification method by Lin, et al was directing at verifying the proper operation of a user design, while the user design connected to an external I/O device. The method generates a first model of the user design in software for use in simulation, generates a second model of a portion of the user design in hardware, which is controlled by the first model in the software. More specifically, in this system, the data evaluations in the first model in software and the second model in hardware are synchronized using a software-generated clock. For debugging, the method simulates selected debug test points in software, accelerates selected debug test points in hardware and controls the delivery of data among the first model in software, the second model in hardware, and the external I/O device so that the first model in software has access to all delivered data.
    [0009]In the prior art, designing, debugging, verifying and validating a system that includes a user design integrated with one or more third party IPs is generally difficult, as the user often starts with designing a behavior description or a simulation model of the IP with incomplete control over the IPs logical behavior at the interfaces between the user design and the IPs. In addition, user designs that are specified by behavior simulation models, logic gates and embedded software are extremely difficult to create. In such a system, it is also difficult to isolate system faults. For example, it is difficult to discover errors within an audio or video output data stream, unless the user can “hear” or “see” the rendered audible or visual results. A conventional design verification and validation method therefore prototypes (architects) the system behavior in an EDA (EDA) simulation environment to verify the numerous interface functions. Afterwards, the system separately embodies the EDA-simulated logic into custom application reference board-based validation environments to “hear” or “see” the audible or visual results. The final step in the prototyping involves incorporating the logic into packaged electronic devices according to product-level electrical specification. During this conventional process of design verification and validation, for example, incorrectly behaving output signals of an audio or video decoder due to logic, algorithmic or software programming errors in the user design may manifest themselves in unpredictable audio or display behavior. For a complicated system, unpredictable behavior potentially caused by a logic, algorithmic or software programming error is extremely difficult to diagnose and isolate, whether in the EDA simulation or the application reference board environment. Therefore, a design verification and validation method with associated tools that allows the user (1) to integrate his EDA prototyping simulation process directly with his printed circuit board (PCB) prototype, (2) to quickly isolate or fix design faults, and (3) to quickly verify and validates his PCB prototype in an integrated environment is highly desirable. In essence, such a design verification and validation method would provide the user with a high throughput, end-to-end solution from design verification to system validation.
    [0010]SUMMARY OF THE INVENTION
    [0011]A method for progressively prototyping and validating a customer's electronic system design (ESD) with design data is provided, according to one embodiment of the present invention. The customer's ESD data is partitioned into numerous hierarchical design elements HDE i (i=1, 2, . . . , M) together with their respective interconnecting networks and test benches. The ESD data typically couples and interacts with numerous customer peripheral devices CPD j (j=1, 2, . . . , N) via their corresponding peripheral interface terminals PIT j (j=1, 2, . . . , N), thus forming correspondingly interconnected hierarchical system elements HSE k (k=1, 2, . . . , K with k≧1) interacting with one another according to a pre-defined hierarchically structured, functional validation specification. The hierarchical system elements HSE k further form a number of system hierarchy levels SHL m (m=1, 2, . . . , P). According to one embodiment of the present invention, the method includes:
    [0012]a) Providing a reprogrammable logic device (RPLD) with (i) an RPLD-interface for configuring and programming the RPLD, and (ii) programmable external interfaces PXIF j (j=1, 2, . . . , N) respectively connected to the PIT j (j=1, 2, . . . , N). b) Providing a simulation software tool that can (i) read the design data, (ii) simulate and (iii) verify each of the HDE i in conjunction with the test benches. c) Disabling all the PXIF j via the RPLD-interface, and for each PXIF k so disabled, (i) identifying those HDE i 's having a network connection to the PXIF k , and (ii) appends their test benches with stimuli and responses to form appended test benches that reflect the interactive behavior of the corresponding CPD k . d) Progressively verifying and validating all the HSE k by: d1) Identifying a set of HSE candidates which are not yet verified and validated and each of which having no interconnection to another HSE at a lower system hierarchy level that is not yet verified and validated. d2) Verifying and validating each member of the HSE candidate set together with its corresponding hierarchical design elements and customer peripheral devices. (Accomplishing this verifying and validating procedure using the simulation software, the test benches, appended test benches, RPLD and functional validation specification.) d3) Repeating the above steps d1) and d2) till all members of the set HSE k (k=1, 2, . . . , K) are verified and validated with the now completed RPLD prototype against the functional validation specification.
    [0013]When an HSE candidate member only includes an HDE, verifying and validating the HSE candidate member further involves verifying the HDE with the simulation software, and its respective test bench. Next, the method converts, by configuring and programming the RPLD, the verified HDE into a corresponding programmed hierarchical element in the RPLD. The method then places and routes all programmed hierarchical elements according to their respective interconnecting networks on the RPLD.
    [0014]When an HSE candidate member includes an HDE and its coupled CPD, validating the HSE candidate member further involves:
    [0015]d21) Verifying the HDE using the simulation software and its respective appended test bench. Thereafter, the method converts, by configuring and programming the RPLD, the verified HDE into a corresponding programmed hierarchical element in the RPLD. The method then places and routes all programmed hierarchical elements according to their respective interconnecting networks on the RPLD. d22) Removing the respective appended test benches and enabling a PXIF corresponding to the coupled CPD via the RPLD-interface. d23) Validating those portions of the functional validation specification corresponding to the RPLD and a subset of the CPD j (j=1, 2, . . . , N) corresponding to an updated set of enabled PXIF.
    [0016]While progressively verifying and validating, all the HSE k normally proceeds in an upward direction along the system hierarchy levels towards the root or roots. Upon detection of an error during the verification or validation process, the method temporarily verifies and validates the HSE k in a downward direction along the system hierarchy levels towards the leaves, until the bug or bugs in the ESD causing the detected error are discovered and fixed. In one embodiment which monitors the HSE k behavior, the method inserts a number of error detectors into the ESD at the SHL k corresponding to the HSE k and sets up a quarantine area for further bug fixing.
    [0017]To increase the prototyping and validating throughput for the HSE candidate set with the simulation software, the method identifies a set of hierarchical system elements with no overlapping of their respective input/output signals (“parallel hierarchical system elements”). The method then simultaneously verifies and validates these parallel hierarchical system elements using the simulation software.
    [0018]For those hierarchical system elements under verification whose input signals include a signal coming from an already programmed hierarchical element, the method samples the signal from the already programmed hierarchical element and then provides the value of the signal to the simulation software. In this way, the method realizes a hybrid prototyping process of joint hardware software simulation with much increased prototyping throughput. Finite logic and hardware propagation delays may lead to a false signal being sampled from the programmed hierarchical element. Therefore, while converting a verified HDE into its corresponding programmed hierarchical element, the method programs the RPLD to provide an output data ready signal as an output signal of the programmed hierarchical element to indicate the validity state of the output signals following a change of any of its input signals. The method then conditionally samples the signal according to the state of the output data ready signal.
    [0019]For those customers already in possession of a customer RPLD, the method includes, via programming:
    [0020](a) Inserting and configuring the RPLD-interface into the customer RPLD. (b) Inserting and configuring the PXIF j (j=1, 2, . . . , N) into the customer RPLD and respectively and (c) connecting them to the PIT j (j=1, 2, . . . , N), thus realizing a cost-saving related to the RPLD.
    [0021]In a more specific embodiment under the current invention method, the RPLD-interface includes a set of vector generator, configuration interface, error detectors and error alarm.
    [0022]For those customers already in possession of a test pattern generator and a customer simulation software tool capable of simulating and verifying the hierarchical design elements, the method simply provides a vector generation tool, which interfaces with the customer simulation software and the test pattern generator to interact with the design data at a functional level, thus realizing a cost-saving in the test pattern generator and the simulation software tool.
    [0023]According to one embodiment of the current invention, the vector generation tool includes a set of configurable simulator interfaces, a configurable test pattern generator, an error detector and an error analyzer.
    [0024]According to one embodiment of the current invention, the RPLD is a programmably interconnected array of field programmable gate arrays (FPGAs).
    [0025]These and other aspects of the present invention and their numerous embodiments are further made apparent, in the remainder of the present description, to those of ordinary skill in the art.
    [0026]BRIEF DESCRIPTION OF THE DRAWINGS In order to more fully describe numerous embodiments of the present invention, reference is made to the accompanying drawings. However, these drawings are not to be considered limitations in the scope of the invention, but are merely illustrative: FIG. 1A illustrates the end goal of the present invention that is a customer's verified and validated electronic system prototype including a number of customer peripheral devices all in a hardware environment; FIG. 1B illustrates, as a side-product of the end goal of the present invention, a customer's verified electronic system design in an EDA software simulation environment corresponding to FIG. 1A but excluding its customer peripheral devices; FIG. 2A through FIG. 8B together illustrate the present invention method of progressively verifying and validating the customer's electronic system design and prototype concurrently in the hardware and the EDA software simulation environment; and, in more progressive details; FIG. 2A and FIG. 2B together illustrate a first initialized state, under the present invention, of the hardware and the EDA software before any verification and validation progress; FIG. 3A and FIG. 3B together illustrate a second state of progression of the hardware and the EDA software upon completion of the verification and validation process at system hierarchy level one; FIG. 4A and FIG. 4B together illustrate a third state of progression of the hardware and the EDA software upon completion of the verification and validation process at system hierarchy level two; FIG. 4C , FIG. 4D and FIG. 4E together illustrate a hybrid prototyping process of joint hardware software simulation under the present invention while verifying a hierarchical design element HDE 10 between the second state and the third state of progression of the hardware and the EDA software; FIG. 5A and FIG. 5B together illustrate a fourth state of progression of the hardware and the EDA software upon completion of the verification and validation process at system hierarchy level three; FIG. 6A and FIG. 6B together illustrate a fifth state of progression of the hardware and the EDA software upon completion of the verification and validation process at system hierarchy level four; FIG. 7A through FIG. 7G together illustrate an error detection and bug fixing procedure under the present invention while validating a hierarchical system element HSE 12 with an enabled customer peripheral device CPD 2 (RF transceiver) between the third state and the fourth state of progression of the hardware and the EDA software; and FIG. 8A and FIG. 8B together illustrate a sixth state of progression of the hardware and the EDA software upon completion of the final verification and validation process at system hierarchy level five.
    [0027]DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS
    [0028]The description herein, in conjunction with the drawings, merely focus on one or more currently preferred embodiments of the present invention and also describe some exemplary optional features and alternative embodiments. The description and drawings are presented to illustrate and, as such, are not limitations of the present invention. Thus, upon consideration of this disclosure, those of ordinary skill in the art would readily recognize variations, modifications, and alternatives. Such variations, modifications and alternatives should be understood to be also within the scope of the present invention.
    [0029]FIG. 1A illustrates the end goal of the present invention that is a customer's verified and validated electronic system prototype 10 including a number of coupled customer's existing peripheral devices (CPD) CPD 1 12 , CPD 2 14 , CPD 3 16 , CPD 4 18 and CPD 5 20 all in a hardware environment. FIG. 1B illustrates, as a side-product of the end goal of the present invention, the customer's verified electronic system design (ESD) 200 in an EDA software simulation environment corresponding to FIG. 1A but excluding any direct physical connection to its customer peripheral devices. For the purpose of this description, the words “verification” and “validation” refer respectively to “verifying the ESD in an EDA software simulation environment” and “validating the electronic system prototype in a physical hardware environment”.
    [0030]As shown in FIG. 1B , the design data of the electronic system design 200 is partitioned into numerous hierarchical design elements (HDE) HDE 1 22 b , HDE 2 24 b , HDE 3 26 b , . . . , HDE 18 56 b together with their respective interconnecting networks. In this example, five system hierarchical levels (SHL) SHL 1 71 , SHL 2 72 , SHL 3 73 , SHL 4 74 and SHL 5 75 are illustrated with:
    [0031]SHL 1 71 corresponds to gate level design of lowest complexity. SHL 2 72 corresponds to function level design of a first higher complexity. SHL 3 73 corresponds to block level design of a second higher complexity. SHL 4 74 corresponds to subsystem level design of a third higher complexity. SHL 5 75 corresponds a top system level design of the highest complexity. Thus, HDE 1 22 b through HDE 7 34 b belong to the system hierarchy level SHL 1 71 wherein, for example, the HDE 2 24 b itself may be an interconnected group of ten logic gates, the HDE 5 30 b itself may be a group of twelve flip flops, and the HDE 7 34 b may be a group of twenty serially connected shift registers. HDE 8 36 b through HDE 11 42 b belong to the system hierarchy level SHL 2 72 wherein, for example, the HDE 9 38 b may be a 12-bit by 12-bit multiplier and the HDE 11 42 b may be a 16-bit audio digital-to-analog converter (DAC). HDE 12 44 b through HDE 15 50 b belong to the system hierarchy level SHL 3 73 wherein, for example, the HDE 12 44 b may be a third party digital RF signal processing IP and the HDE 14 48 b may be a third party video image enhancement IP. HDE 16 52 b and HDE 17 54 b belong to the system hierarchy level SHL 4 74 wherein, for example, the HDE 16 52 b may be an HDD (hard disk drive) controller and the HDE 17 54 b may be a video display controller. Finally, HDE 18 56 b may be a portable operating system (OS) at the highest system hierarchy level SHL 5 75 .
    [0032]As examples of the interconnecting networks among the hierarchical design elements, both HDE 1 22 b and HDE 2 24 b are interconnected to and form part of the HDE 8 36 b via network signal S 1-8 and network signal S 2-8 . As a second example, both HDE 10 40 b and HDE 11 42 b are interconnected to and form part of the HDE 14 48 b via network signal S 10-14 and network signal S 11-14 . As a third example, both HDE 16 52 b and HDE 17 54 b are interconnected to and form part of the HDE 18 56 b via network signal S 16-18 and network signal S 17-18 . In general, network signals are bi-directional and each include multiple signal lines effecting stimuli and responses amongst the hierarchical design elements. Therefore, in an EDA software simulation environment the network signals of each hierarchical design element can be modeled as its test bench, simulated and verified accordingly. For example, the network signals S 3-9 , S 4-9 and S 9-13 can be modeled as the test bench for the 12-bit by 12-bit multiplier HDE 9 38 b , simulated and verified accordingly. As a graphical convention of the present invention, each HDE box is first shown without a fill pattern before any verification with an EDA simulation, but subsequently shown filled with a cross-hatch pattern following verification with an EDA simulation. In the art, the design data of the electronic system design 200 can be expressed in a variety of EDA languages, such as VHDL, Verilog, System C, to name a few. Thus, a simulation software tool is presumed capable of reading the design data, simulating and then verifying each of the HDEs together with their test benches. Technically, the simulation software tool may be cycle-based, transaction-based, formal-based 2 , or a combination thereof. A few examples of such simulation software tool include Incisive Simulator from Cadence Design Systems Inc., VCS from Synopsys Inc. and ModelSim from Mentor Graphics Corporation. 2 For more detailed description, see published US patent applications US 20050114809 entitled “Design verification using formal techniques” and US 20040153308 entitled “Method and system for design verification using proof-based abstraction” these are hereby incorporated for reference.
    [0033]Corresponding to the hierarchical partition of the design data into the above HDEs and their respective interconnecting networks, the customer's verified and validated electronic system prototype 10 of FIG. 1A also embodies similar hierarchical partition in hardware, now individually named hierarchical system elements (HSE), with the exception of some differences due to the coupled CPDs. Thus, HSE 1 22 a through HSE 7 34 a represent the electronic hardware embodiment of the HDE 1 22 b through the HDE 7 34 b . HSE 8 36 a through HSE 10 40 a represent the electronic hardware embodiment of the HDE 8 36 b through the HDE 10 40 b . However, HSE 1 142 a represents the electronic hardware embodiment of the HDE 11 42 b together with its coupled CPD 1 12 . Likewise, HSE 17 54 a represents the electronic hardware embodiment of the HDE 17 54 b together with its coupled CPD 4 18 , etc. The fact that both HDE 1 22 b and HDE 2 24 b form part of the HDE 8 36 b is now indicated by enclosing both HSE 1 22 a and HSE 2 24 a within the HSE 8 36 a in the electronic system prototype 10 . Likewise, the fact that both HDE 10 40 b and HDE 11 42 b form part of the HDE 14 48 b is now indicated by enclosing both HSE 10 40 a and HSE 11 42 a within the HSE 14 48 a in the electronic system prototype 10 . In FIG. 1A , all programmed HSEs have been placed and routed according to their respective interconnecting networks. As a graphical convention of the present invention, each HSE box is bordered with dashed line before any verification and validation with EDA simulation and hardware validation, but subsequently bordered with dash-dot line (_._.) following verification and validation with EDA simulation and hardware validation. The following are examples of the various CPDs illustrated in FIG. 1A :
    [0034]CPD 1 12 : Audio Device. CPD 2 14 : radio frequency (RF) Transceiver. CPD 3 16 : hard disk drive (HDD) drive. CPD 4 18 : Video Device. CPD 5 20 : microprocessor unit (MPU) & Memory. To those skilled in the art, a successful hardware validation requires that the set of HSEs interact with one another and with the CPDs according to a pre-defined hierarchically structured functional validation specification. As an example, the functional validation specification may include the following:
    [0035]Upon occurrence of an RF-based audio signal at the CPD 2 14 (e.g., an RF transceiver), the same received audio signal as buffered through the CPD 3 16 (e.g., an HDD Drive) and processed with the HDE 18 56 b (e.g., a portable OS) should commence playback within 2 seconds.
    [0036]Under the present invention the electronic system prototype 10 , excluding the numerous CPDs, should be implemented with a reprogrammable logic device (RPLD) such as a programmably interconnected array of field programmable gate arrays (FPGAs). The RPLD should also have an RPLD-interface for its configuration and programming. The RPLD should further have a number of programmable external interfaces PXIF, either enabled or disabled via programming through its RPLD-interface, for connection to the respective CPDs. Thus, as shown in FIG. 1A :
    [0037]The HSE 11 42 a has an HDE 11 42 b and a CPD 1 12 , the CPD 1 12 has a peripheral interface terminal (PIT) PIT 1 12 a connected to an enabled PXIF 1 13 c . In this state the enabled PXIF 1 13 c thus effects a coupling between the CPD 1 12 and the HDE 11 42 b. The HSE 17 54 a has an HDE 17 54 b and a CPD 4 18 , the CPD 4 18 has a PIT 4 18 a connected to an enabled PXIF 4 19 C. In this state the enabled PXIF 4 19 c thus effects a coupling between the CPD 4 18 and the HDE 17 54 b. The HSE 18 56 a has an HDE 18 56 b and a CPD 5 20 , the CPD 5 20 has a PIT 5 20 a connected to an enabled PXIF 5 21 c . In this state the enabled PXIF 5 21 c thus effects a coupling between the CPD 5 20 and the HDE 18 56 b , etc.
    [0038]In view of the above and as part of the present invention, the following conditions pertaining to the states of a PXIF are introduced and illustrated using CPD 1 12 as an example:
    [0039](A) Simply disable PXIF 1 , the resulting disabled PXIF 1 is graphically illustrated by: (B) Disable PXIF 1 but then append the test bench of HDE 11 42 b with a stimuli and responses to form an appended test bench for HDE 11 42 b . In this case, the appended stimuli and responses should reflect the interactive behavior of the CPD 1 12 . The resulting disabled PXIF 1 is graphically illustrated by: (C) Enable PXIF 1 , the resulting enabled PXIF 1 is graphically illustrated by:
    [0040]With this scheme, the present invention allows an initial simulation and verification of each HDE in an EDA software simulation environment under condition (B) without the major complication of its coupled CPD, if such a CPD exists. Afterwards, the HDE is programmed into an HSE and the PXIF can be enabled to allow validation of the HSE under condition (C) with its coupled CPD. Especially for a highly complex HDD Drive like the CPD 3 16 , the appended stimuli and responses for reflecting the interactive behavior of the CPD 3 16 can only expect to be its rough approximation for the initial simulation and verification of HDE 16 52 b . The rough approximation does not present a real problem as the CPD 3 16 will be coupled to the HSE 16 52 a during its validation phase.
    [0041]FIG. 2A through FIG. 8B together illustrate within the scope of the present invention a method for progressively verifying and validating the customer's electronic system design 200 and electronic system prototype 10 concurrently in the hardware and the EDA software simulation environment.
    [0042]FIG. 2A and FIG. 2B together illustrate a first initialized state of the hardware and the EDA software before any verification and validation. As explained above, all the PXIFs are disabled (disabled PXIF 1 13 a , disabled PXIF 2 15 a , disabled PXIF 3 17 a , disabled PXIF 4 19 a and disabled PXIF 5 21 a ) under condition (B) to allow an initial simulation and verification of each HDE in an EDA software simulation environment without the major complication of its coupled CPD. Notice each HDE box is shown without a fill pattern in FIG. 2B and each HSE box is bordered with dashed line in FIG. 2A .
    [0043]FIG. 3A and FIG. 3B together illustrate a second state of progression of the hardware and the EDA software upon completion of the verification and validation process at system hierarchy level SHL 1 71 , the lowest hierarchy of the customer's electronic system design 200 . Here, the HDE 1 22 b through HDE 7 34 b together with their respective test benches have been simulated and verified with a simulation software tool. More specifically, a test bench for the HDE 3 26 b models the network signal S 3-9 . A test bench for the HDE 7 34 b models the network signal S 7-11 . HDE 1 22 b through HDE 7 34 b do not overlap in their respective network signals (S 1-8 , S 2-8 , S 3-9 , S 4-9 , S 5-10 , S 6-10 , S 7-11 ). Thus HDE 1 22 b through HDE 7 34 b are effectively parallel HDEs. If so desired, HDE 1 22 b through HDE 7 34 b can be simultaneously simulated and verified with a simulation software tool in a multi-processing environment to increase the prototyping throughput. Thereafter, HDE 1 22 b through HDE 7 34 b are configured and programmed, placed and routed into HSE 1 22 a through HSE 7 34 a on an RPLD.
    [0044]FIG. 4A and FIG. 4B together illustrate a third state of progression of the hardware and the EDA software upon completion of the verification and validation process at a higher system hierarchy level SHL 2 72 of the customer's electronic system design 200 . Here, the HDE 8 36 b through HDE 11 42 b together with their respective test benches have been simulated and verified with a simulation software tool. More specifically, a test bench for the HDE 8 36 b models network signals S 1-8 , S 2-8 , S 8-13 . A test bench for the HDE 9 38 b models network signals S 3-9 , S 4-9 , S 9-13 . HDE 8 36 b through HDE 11 42 b do not overlap their respective network signals (S 1-8 , S 2-8 , S 8-13 , S 3-9 , S 4-9 , S 9-13 , S 5-10 , S 6-10 , S 10-14 , S 7-11 , S 11-14 ). Thus HDE 8 36 b through HDE 11 42 b are effectively parallel HDEs. If so desired, HDE 8 36 b through HDE 11 42 b can be simultaneously simulated and verified with a simulation software tool in a multi-processing environment to increase the prototyping throughput. Thereafter, HDE 8 36 b through HDE 11 42 b are configured and programmed, placed and routed into HSE 8 36 a through HSE 11 42 a on an RPLD. In FIG. 4A , the verified HDE 11 42 b is coupled to the CPD 1 12 through an enabled PXIF 1 13 c under condition (C) and a PIT 1 12 a , whereas in FIG. 3A the unverified HDE 11 42 b is separated from the CPD 1 12 through a disabled PXIF 1 13 a under condition (B) and the PIT 1 12 a . This means, as described before, during the simulation and verification of HDE 11 42 b the test bench of HDE 11 42 b has been appended with stimuli and responses to form an appended test bench for HDE 11 42 b with the appended stimuli and responses reflecting the interactive behavior of the CPD 1 12 . After successful verification, the verified HDE 11 42 b is configured and programmed on an RPLD. The appended test bench is then removed and the PXIF 1 enabled (into condition (C)) by programming via the RPLD-interface. Finally, those portions of the functional validation specification corresponding to the as-programmed RPLD and a subset of the CPDs corresponding to an updated set of enabled PXIFs are validated.
    [0045]FIG. 4C , FIG. 4D and FIG. 4E together illustrate a hybrid prototyping process of joint hardware software simulation under the present invention while verifying the HDE 10 40 b between the second state and the third state of progression of the hardware and the EDA software.
    [0046]As indicated in FIG. 4C and FIG. 4D , the HDE 10 40 b under simulation receives its network signals S 5-10 from HDE 5 30 b that has already been verified and programmed into HSE 5 30 a on an RPLD hardware. Likewise, the other network signals S 6-10 are received from HDE 6 32 b that has also been verified and programmed into HSE 6 32 a on an RPLD hardware. Therefore, those portions of the test bench for HDE 10 40 b associated with the network signals S 5-10 can be implemented by sampling the network signals S 5-10 from the already programmed HSE 5 30 a hardware in real-time. The values of the network signals S 5-10 into the simulation software thus realize a hybrid prototyping process of joint hardware and software simulation with increased prototyping throughput (due to hardware acceleration). The increase in prototyping throughput, as compared to a scheme of pure software simulation, is expected to rise correspondingly, as the level of hardware integration of the electronic system prototype 10 advances. At such hardware integration level, pure software simulation with even high performance computers is limited in its throughput. Similarly, those portions of the test bench for HDE 10 40 b associated with the network signals S 6-10 can be implemented by sampling the network signals S 6-10 from the already programmed HSE 6 32 a hardware and providing the values of the network signals S 6-10 into the simulation software. The resulting hybrid simulation environment is illustrated in FIG. 4E where the HDE 10 40 b under simulation receives the network signals S 5-10 from HSE 5 30 a via data paths DP 5-10 80 b and receives the network signals S 6-10 from HSE 6 32 a via data paths DP 6-10 82 b.
    [0047]To prevent the simulation software from sampling a false hardware signal from HSE 5 30 a or HSE 6 32 a due to logic and hardware propagation delays, the HSEs are further programmed to provide output “data ready” signals ODR 5 80 a and ODR 6 82 a . The ODR 5 80 a of HSE 5 30 a indicates the state of validity of its output network signals S 5-10 following a change of any of its input signals. The simulation software then conditionally samples the network signals S 5-10 via the DP 5-10 80 b according to the state of the ODR 5 80 a . Similarly, the ODR 6 82 a of HSE 6 32 a indicates the state of validity of its output network signal network signals S 6-10 following a change of any of its input signals. The simulation software then conditionally samples the network signals S 6-10 via the DP 6-10 82 b data paths according to the state of the ODR 6 82 a . Other HDEs qualified for the described hybrid prototyping process between the second state and the third state of progression of the hardware and the EDA software are HDE 8 36 b , HDE 9 38 b and HDE 11 42 b.
    [0048]FIG. 5A and FIG. 5B together illustrate a fourth state of progression of the hardware and the EDA software upon completion of the verification and validation process at a higher system hierarchy level SHL 3 73 of the customer's electronic system design 200 . Here, the HDE 12 44 b through HDE 15 50 b together with their respective test benches have been simulated and verified with a simulation software tool. If so desired, HDE 12 44 b through HDE 15 50 b can be simultaneously simulated and verified with a simulation software tool in a multi-processing environment to increase the prototyping throughput. Thereafter, HDE 12 44 b through HDE 15 50 b are configured and programmed, placed and routed into HSE 12 44 a through HSE 15 50 a on an RPLD. During the simulation and verification of HDE 12 44 b the test bench of HDE 12 44 b has been appended with stimuli and responses to form an appended test bench for HDE 12 44 b with the appended stimuli and responses reflecting the interactive behavior of the CPD 2 14 . After successful verification, the verified HDE 12 44 b is configured and programmed on an RPLD. The appended test bench is then removed and the PXIF 2 enabled (into condition (C)) by programming via the RPLD-interface. Finally, those portions of the functional validation specification corresponding to the as-programmed RPLD and a subset of the CPDs corresponding to an updated set of enabled PXIFs are validated. The HDEs qualified for the hybrid prototyping process between the third state and the fourth state of progression of the hardware and the EDA software are HDE 12 44 b , HDE 13 46 b and HDE 14 48 b.
    [0049]FIG. 6A and FIG. 6B together illustrate a fifth state of progression of the hardware and the EDA software upon completion of the verification and validation process at a higher system hierarchy level SHL 4 74 of the customer's electronic system design 200 . Here, the HDE 16 52 b through HDE 17 54 b together with their respective test benches have been simulated and verified with a simulation software tool. If so desired, HDE 16 52 b through HDE 17 54 b can be simultaneously simulated and verified with a simulation software tool in a multi-processing environment to increase the prototyping throughput. Thereafter, HDE 16 52 b through HDE 17 54 b are configured and programmed, placed and routed into HSE 16 52 a through HSE 17 54 a on an RPLD. During the simulation and verification of HDE 16 52 b the test bench of HDE 16 52 b has been appended with stimuli and responses to form an appended test bench for HDE 16 52 b with the appended stimuli and responses reflecting the interactive behavior of the CPD 3 16 . After successful verification, the verified HDE 16 52 b is configured and programmed on an RPLD. The appended test bench is then removed and the PXIF 3 enabled (into condition (C)) by programming via the RPLD-interface. During the simulation and verification of HDE 17 54 b the test bench of HDE 17 54 b has been appended with stimuli and responses to form an appended test bench for HDE 17 54 b with the appended stimuli and responses reflecting the interactive behavior of the CPD 4 18 . After successful verification, the verified HDE 17 54 b is configured and programmed on an RPLD. The appended test bench is then removed and the PXIF 4 enabled (into condition (C)) by programming via the RPLD-interface. Finally, those portions of the functional validation specification corresponding to the as-programmed RPLD and a subset of the CPDs corresponding to an updated set of enabled PXIFs are validated. The HDEs qualified for the hybrid prototyping process between the fourth state and the fifth state of progression of the hardware and the EDA software are HDE 16 52 b and HDE 17 54 b.
    [0050]FIG. 7A through FIG. 7G together illustrate an error detection and bug fixing procedure under the present invention while validating an HSE 12 44 a with an enabled PXIF 2 15 c for CPD 2 14 (e.g., an RF transceiver) between the third state and the fourth state of progression of the hardware and the EDA software. While validating the HSE 12 44 a at SHL 3 73 , an error is encountered that is apparently related to audio data reception and playback through the HSE 12 44 a and the HSE 11 42 a . Notice that HSE 12 44 a is coupled to CPD 2 14 via an enabled PXIF 2 15 c while HSE 11 42 a is coupled to CPD 1 12 (Audio Device) via an enabled PXIF 1 13 c . To accurately locate the error source within the electronic system design 200 , an error detector 100 is inserted inside HSE 12 44 a by programming the RPLD. A second error detector 102 is also inserted inside HSE 11 42 a by programming the RPLD as illustrated in FIG. 7A . In FIG. 7B , upon further validating activity, as no error inside HSE 12 44 a is detected by the error detector 100 , error detector 100 is therefore removed by programming the RPLD. On the other hand, the error detector 102 does detect an error inside HSE 11 42 a and hence a quarantine area 120 is set up inside HSE 11 42 a at SHL 2 72 , again by programming the RPLD, to refine the location of the error source. In FIG. 7C , upon further validating activity with analysis using the error detector 102 and the quarantine area 120 a bug is located to be inside HSE 7 34 a at the lowest SHL 1 71 . Thus, another error detector 104 and another quarantine area 122 are created inside HSE 7 34 a to pin point the precise location of the bug. As the bug ultimately resides in the electronic system design 200 , FIG. 7D and FIG. 7E together illustrate a temporary retreat back to the EDA software simulation environment to fix the bug. In FIG. 7D the CPD 1 12 is, through the disabled PXIF 1 13 a under condition (B), decoupled from the HDE 11 42 b to facilitate its software simulation with a correspondingly appended test bench. In FIG. 7E both HDE 7 34 b and HDE 11 42 b are re-simulated and re-verified after the bug inside HDE 7 34 b is fixed at SHL 1 71 . Afterwards, FIG. 7F illustrates the re-validation of HSE 11 42 a at SHL 2 72 , with a re-enabled PXIF 1 13 c coupling the CPD 1 12 in the presence of the error detector 102 . As no error is found this time, the error detector 102 is removed and FIG. 7G illustrates the now successful validation of HSE 12 44 a at SHL 3 73 with the re-enabled PXIF 2 15 c for CPD 2 14 (RF transceiver).
    [0051]FIG. 8A and FIG. 8B together illustrate a sixth state of progression of the hardware and the EDA software upon completion of the verification and validation process at the highest system hierarchy level SHL 5 75 of the customer's electronic system design 200 . Here, HDE 18 56 b together with its test bench have been simulated and verified with a simulation software tool. Thereafter, HDE 18 56 b is configured and programmed, placed and routed into HSE 18 56 a on the RPLD. During the simulation and verification of HDE 18 56 b the test bench of HDE 18 56 b has been appended with stimuli and responses to form an appended test bench for HDE 18 56 b with the appended stimuli and responses reflecting the interactive behavior of CPD 5 20 . After successful verification, the verified HDE 18 56 b is configured and programmed on the RPLD. The appended test bench is then removed and the PXIF 5 enabled (into condition (C)) by programming via the RPLD-interface. The electronic system prototype 10 is then validated against the whole functional validation specification—i.e., the so-built prototype in RPLD expects to become the product upon final product-level packaging. Here again, HDE 18 56 b is qualified for the hybrid prototyping process between the fifth state and the sixth state of progression of the hardware and the EDA software. While the CPD 5 20 (MPU & Memory) is shown last enabled during the validation process, in many cases of validating a complex multi-media device CPD (e.g., the CPD 1 12 audio device) with high significance, the CPD 5 20 (MPU & Memory) should also be enabled, so as to be able to use the CPD 5 20 to program or play the CPD 1 12 (Audio Device) for validation.
    [0052]As a general remark, while the present invention has been described in terms of the following specific system hierarchy levels:
    [0053]SHL 1 71 : gate. SHL 2 72 : function. SHL 3 73 : block. SHL 4 74 : subsystem. SHL 5 75 : system. To those skilled in the art the present invention method is applicable to other abstraction of system hierarchy levels as well. The following lists a few examples of such other system hierarchy levels: Transistor, switch, logic (AND, OR, XOR), function (adder, multiplier, arithmetic logic unit (ALU)), behavior (interaction between functions).
    [0054]On the hardware side, for those customers already in possession of a customer RPLD, only the following steps need to be carried out to make the customer RPLD usable under the present invention:
    [0055]1. Inserting and configuring, via programming, the RPLD-interface into the customer RPLD. 2. Inserting and configuring, via programming, the PXIFs into the customer RPLD and respectively connecting them to the PITs. In this way, a cost-saving related to the RPLD is realized. In more detail, inserting and configuring the RPLD-interface can include inserting a set of vector generator, configuration interface, error detectors and error alarm into the customer RPLD.
    [0056]On the software side, for customers already in possession of a test pattern generator and a customer simulation software tool capable of simulating and verifying the HDEs, only the following steps need to be carried out to make the customer simulation software usable under the present invention:
    [0057]Providing a vector generation tool that interfaces with the customer simulation software and the test pattern generator to functionally interact with the design data.
    [0058]In this way, a cost-saving related to the test pattern generator and the simulation software tool is realized. In more detail, providing the vector generation tool can include providing a set of configurable simulator interface, configurable test pattern generator, error detector and error analyzer.
    [0059]While the description above contains many specificities, these specificities should not be constructed as accordingly limiting the scope of the present invention but as merely providing illustrations of numerous presently preferred embodiments of this invention. To those skilled in the art, a method of progressively simulating, prototyping and validating a customer's electronic system design on a reprogrammable logic device with attached customer peripheral devices is invented for general application. Throughout the description and drawings, numerous exemplary embodiments were given with reference to specific configurations. It will be appreciated by those of ordinary skill in the art that the present invention can be embodied in numerous other specific forms and those of ordinary skill in the art would be able to practice such other embodiments without undue experimentation. The scope of the present invention, for the purpose of the present patent document, is hence not limited merely to the specific exemplary embodiments of the foregoing description, but rather is indicated by the following claims. Any and all modifications that come within the meaning and range of equivalents within the claims are intended to be considered as being embraced within the spirit and scope of the present invention.
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