专

多足式机器人足端压力传感器

12660058768U

发明人

罗庆生, 韩宝玲, 赵小川, 张杨, 汪强

受让人

北京理工大学

申请人

Kiyoshi Kasatani, Tsuyoshi Shigemasa

申请号

01239

申请日

1985-09-26

公开(公告)号

12660058768U

公开(公告)日

2001-05-30

IPC分类号

A01N065/12A01N065/24A01N065/40A61P031/04

CPC分类号

优先权号

005670

优先权日

2013-07-22

摘要

Devices, systems, and methods for repositioning organs, such as the rectum, during radiation therapy treatments, are described.

权利要求

1. A helmet protector used in combination with a conventional helmet having a hard helmet outer layer adapted to be exposed to the atmosphere and configured to directly contact with another hard helmet outer layer of another helmet or another helmet protector when being worn by a user, the helmet protector comprising: a helmet protector cover, the helmet protector cover comprising a hard helmet protector layer, the helmet protector cover surrounding at least a portion of the helmet and defining an air space extending between the hard helmet protector cover layer and the hard helmet outer layer when the helmet protector is installed onto the helmet, the helmet protector cover having at least one opening providing an air passageway from the air space to the atmosphere located outside the helmet protector; and a plurality of spacers separating the helmet protector cover away from the helmet when the helmet protector is installed directly on the hard helmet outer layer of the conventional helmet, each of the plurality of spacers being separate discrete spacers spaced apart from each other and located at different positions on the helmet protector cover, and bridging the helmet and helmet protector cover through the air space when the helmet protector is installed on the helmet, wherein the air space surrounds the spacers and is unobstructed between the hard layer of the helmet protector cover and the hard helmet outer layer when the helmet protector is installed on the helmet to allow for propagation of waves generated by an impact to the hard outer layer of the helmet protector cover through the unobstructed air space to the hard helmet outer layer of the helmet, which reflects the waves back through the unobstructed air space and then exiting through the at least one passageway of the helmet protector to the outside atmosphere to dissipate energy from the impact to the helmet protector.

2. The helmet protector according to claim 1 , wherein the at least one air passageway is a plurality of openings.

3. The helmet protector according to claim 2 , wherein each spacer is located between a pair of adjacent openings through the helmet cover.

4. The helmet protector according to claim 2 , wherein the plurality of openings are spaced apart on the helmet cover.

5. The helmet protector according to claim 4 , wherein the plurality of openings are arranged in a pattern on the helmet cover.

6. The helmet protector according to claim 5 , wherein the plurality of openings are arranged in a matrix pattern on the helmet cover.

7. The helmet protector according to claim 6 , wherein each spacer is located between four openings in a square arrangement of the matrix pattern on the helmet cover.

8. The helmet protector according to claim 1 , wherein the at least one air passageway is a round through hole in the helmet cover.

9. The helmet protector according to claim 1 , wherein the at least one opening air passageway is configured to allow a shock wave to exit the air space through the helmet cover.

10. The helmet protector according to claim 1 , wherein the hard outer layer of the helmet cover is a single layer made of the hard material.

11. The helmet protector according to claim 10 , wherein the at least one connector is configured to removably connect the helmet protector to the helmet.

12. The helmet protector according to claim 1 , further comprising at least one connector for connecting the helmet protector to the helmet.

13. The helmet protector according to claim 12 , wherein the at least one connector is configured to grip a lower edge of the helmet to retain the helmet protector onto the helmet.

14. The helmet protector according to claim 1 , wherein the at least one connector is a plurality of connectors.

15. The helmet protector according to claim 14 , wherein the plurality of connectors comprise a pair of side connectors and a front connector and a rear connector.

16. The helmet protector according to claim 1 , wherein the helmet protector is configured so that the helmet nests within the helmet protector.

17. The helmet protector according to claim 16 , wherein the air space and spacers separate the entire helmet cover from the helmet when the helmet cover is installed on the helmet.

18. The helmet protector according to claim 1 , wherein at least one spacer is located adjacent to a front edge of the helmet protector.

19. The helmet protector according to claim 1 , wherein at least one spacer holds the helmet cover off or away from an outer surface of the helmet to provide a side opening between the air space and atmosphere.

20. The helmet protector according to claim 1 , wherein each spacer is attached inside the helmet protector.

21. A helmet protector comprising the conventional helmet and the helmet protector according to claim 1 , the helmet protector being fitted onto the conventional helmet.

22. The helmet protector according to claim 1 , wherein the spacers are circular-shaped and the air space surrounds round sides of the spacers within the air space.

23. A helmet protector used in combination with a conventional helmet having a hard helmet outer layer adapted to be exposed to the atmosphere and configured to directly contact with another hard helmet outer layer of a helmet or another helmet protector when being worn by a user, the helmet protector comprising: a helmet protector cover, the helmet protector cover comprising a hard helmet protector cover layer, the helmet protector cover surrounding at least a portion of the helmet and defining an air space extending between the hard helmet protector cover layer and the hard helmet outer layer when the helmet protector is installed onto the helmet, the helmet protector cover comprising a plurality of openings defined by through holes providing a plurality of air passageways from the air space to the atmosphere located outside the helmet protector; and a plurality of spacers separating the helmet protector cover from the helmet when the helmet protector is installed directly on the hard helmet outer layer of the conventional helmet, each of the plurality of spacers being separate discrete spacers spaced apart from each other and located at different positions on the helmet protector cover, and bridging the helmet and the helmet protector cover through the air space when the helmet protector is installed on the helmet, the plurality of spacers being located at different positions on the helmet protector cover relative to locations of the through holes, wherein the air space surrounds the spacers and is unobstructed between the hard helmet protector cover and the hard helmet outer layer when the helmet protector is installed on the helmet to allow for propagation of waves generated by an impact to the helmet protector cover through the unobstructed air space to the hard helmet outer layer, which reflects the waves back through the unobstructed air space and then exiting through the plurality of openings of the helmet protector cover to dissipate energy from the impact to the helmet protector.

说明书

[0001]CROSS REFERENCE TO RELATED APPLICATION This application is a divisional of application Ser. No. 10/485,139 filed Sep. 2, 2004 now U.S. Pat. No. 7,053,480 entitled “METHOD FOR TESTING A CHIP WITH A PACKAGE AND FOR MOUNTING THE PACKAGE ON A BOARD”.

[0002]BACKGROUND OF THE INVENTION The invention relates to the field of semiconductor packaging and testing, and in particular to mounting an integrated circuit that has been tested on a board, wherein the adjacent connecting pins of the integrated circuit are in an inline arrangement. In order to keep the dimensions small for the package of a chip with multiple connecting pins (e.g., 88 pins), the connecting pins are arranged in line as close as possible. However, a minimum spacing must still be maintained since the space between associated holes on a board for insertion of the connecting pins may not be arbitrarily reduced. As the spacing of the holes and conducting lines on the board becomes closer, the process of fabricating a board becomes more complex and expensive. In addition, there is the risk that close spacing of the holes on the board will cause the connecting pins to short out during the soldering process. One technique for increasing hole spacing on the board is to configure the connecting pins of the package by bending some of the connecting pins or, for example, by inwardly offsetting every second connecting pin. However, the advantage of greater hole spacing on the board is counteracted by the disadvantages of requiring a special test socket to test the chips and requiring an expensive packaging mechanism. Specifically, the packaging mechanism must be designed such that the connecting pins are not bent out of their precise alignment. Therefore, there is a need for a method of testing and mounting the package on a board in such a way that simple and inexpensively produced test sockets are sufficient for testing, and similarly simple and inexpensively produced packaging mechanisms are sufficient for packaging, while at the same time achieving an offset arrangement for the connecting pins.

[0003]SUMMARY OF THE INVENTION Briefly, according to an aspect of the invention, an integrated circuit that includes a die mounted within a package containing a plurality of input/output pins is tested by placing the integrated circuit into a test socket of automatic test equipment. Prior to the tested integrated circuit being mounted on a board, a portion of the plurality of input/output pins are bent from their inline position to an offset position. The integrated circuit with its inline connecting pins is inserted into a test socket for testing. At least one connecting pin is bent inward using a bending tool immediately before insertion of the connecting pins of the integrated circuit into the holes of the board, in order to achieve an offset arrangement of the connecting pins. The integrated circuit includes inline connecting pins (i.e., individuals skilled in the art frequently use the expression “dual inline”), and the integrated circuit is tested in this state. The integrated circuit to be tested is inserted into a test socket. A first advantage is that relatively inexpensive test sockets may be utilized to test the chips. A second advantage is that even inexpensive packaging mechanisms are sufficient for storing and transporting the chips. Additionally, at least one connecting pin, preferably every second connecting pin, is bent inward by the bending tool immediately before insertion of the connecting pins of the integrated circuit into the board in order to form an offset arrangement of the connecting pins. The invention thus combines the advantages of a package in which its connecting pins are in an inline arrangement with those of a package in which its connecting pins are in an offset arrangement. Electrical testing of the chip may thus be of a simple design since inexpensively produced test sockets are sufficient for the task. In addition, standard packaging mechanisms may be employed to package the package. Subsequent alignment of the connecting pins is simplified since the connecting pins are not bent into the offset arrangement until immediately before insertion into the board, rather than at the fabrication stage of the package. These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings.

[0004]BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a flowchart illustration of a method of testing an integrated circuit and bending selected external input/output pins of the integrated circuit and mounting the integrated circuit with selected external input/output pins bent an angle with respect to the inline position of the pins; FIGS. 1B-1F are simplified illustrations of the integrated circuit during the steps illustrated in FIG. 1A ; FIG. 2 is a top view illustration of an embodiment of a package with the bending tool attached; FIG. 3 is a front view illustration of the package of FIG. 2 with the bending tool attached; FIG. 4 is a front view illustration of an embodiment of a package; FIG. 5 is a section view of a board having holes for the connecting pins; and FIGS. 6A-6D illustrate another example of an integrated circuit.

[0005]DETAILED DESCRIPTION OF THE INVENTION FIG. 1A is a flow chart illustration of a method 100 for testing an integrated circuit, bending the pins of the integrated circuit and mounting the integrated circuit. FIGS. 1B-1F are simplified sectional views of the integrated circuit during the steps illustrated in FIG. 1A . Referring to FIGS. 1A-1F , in step 102 inline connecting pins 1 of an integrated circuit that includes a die (not shown) and a package 2 containing the die, are input to a test socket 3 as shown in FIG. 1B . In step 104 , any rework that may be required on the package 2 or the chip is performed. The package 2 is then placed in a packaging mechanism such as a guide brace 4 and shipped in step 106 . Immediately before the package 2 is mounted on a board 5 , every second connecting pin 12 , for example, is bent inward by a bending tool 6 , while the remaining connecting pins 11 are left unmodified. The connecting pins 11 and 12 are inserted into associated holes 71 - 72 of the board 5 , preferably, by the bending tool 6 . FIG. 2 is a top view illustration of the package 2 , along with the connecting pins 11 and 12 , and with the bending tool 6 attached. FIG. 3 is a front view illustration of the package 2 with the connecting pins 11 and 12 , and with the bending tool 6 attached. Every second connecting pin 12 is bent inward, while the remaining connecting pins 11 remain bent outward or are oriented vertically, as is the case during fabrication of the package 2 . FIG. 4 is a front view of the package 2 , with the first connecting pins 11 bent outward and the second connecting pins 12 bent inward, including dimensional details. The spacing between the vertical pins on the package is 19.05 mm. The second connecting pins 12 are bent 0.4 mm inward from the vertical, while the first or remaining connecting pins 11 are bent 0.87 mm outward. FIG. 5 is a section of the board 5 having first holes 71 for the outwardly bent first connecting pins 11 , and second holes 72 for the inwardly bent second connecting pins 12 . The first and second holes 71 and 72 are offset relative to each other by 1.27 mm. The spacing of the inline holes 71 and 72 is 2.54 mm. The spacing between two offset holes 71 and 72 is chosen as 1.8 mm. The connecting pins on the package may be arranged symmetrically relative to the longitudinal center axis and the transverse center axis of the package since this symmetrical arrangement allows for the use of a symmetrical bending tool. It is then irrelevant how the bending tool is placed on the package. It is impossible to bend the connecting pins incorrectly by attaching the bending tool with the improper orientation. The method according to the invention permits the use of packaging mechanisms suitable for the standard PSDIP package. No special packaging mechanisms are required. While the above figures describe an approach in which every second connecting pin is bent inward once, FIG. 6 illustrates another possibility. With this possibility, every second pin 12 is bent 90° downward, relative to the package. Every intermediate pin 11 , on the other hand, is first bent downward by less than 90° relative to the package, for example, by 45°, then subsequently bent by an additional angle, for example, 45°. Although the present invention has been shown and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.

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