The results of an experimental comparison of programs for technologically independent minimization of complexity of multilevel representations of systems of fully defined functions based on the Shannon expansion are described. The main attention is paid to the effectiveness of using, when synthesizing logical circuits, a program that implements an algorithm for solving the problem of extracting from a system of functions such subsystems for which it is advisable to carry out joint minimization of multi-level representations of subsystems in the form of Binary Decision Diagrams, called BDD-representations, and in the form of Boolean net. The complexity of the representation is estimated by the total number of literals of Boolean variables in a set of interrelated logical equations that define a system of Boolean functions. After extracting the subsystems and their joint minimization, the synthesis of logic circuits is carried out in the design library of custom digital CMOS VLSIs, the results are compared in terms of chip area and speed (time delay) on a stream of 39 industrial examples of circuits. It was found that for 20 examples, the subsystem selection algorithm allows one to obtain better solutions than joint or separate minimization of multi-level representations based on Shannon expansion (13 examples). The three best solutions are obtained by applying the well-known Espresso program for minimizing functions in the DNF class, and the three solutions are obtained by the synthesizer using the original (non-optimized) matrix representations of DNF systems of Boolean functions.

Objectives. The purpose of experimental research is to determine the effectiveness of new algorithms for extracting the so-called connected subsystems from formula descriptions of the original system of Boolean functions. Subsequently each of the extracted subsystems is minimized independently of the others, but the functions that make up each connected subsystem are minimized jointly.Methods. Minimization of subsystems is performed in the class of multilevel BDD representations (BDD – Binary Decision Diagram) or Boolean networks. After obtaining minimized descriptions of circuits, specified as a set of interconnected Shannon expansion formulas that correspond to BDD, or as two-operand logical equations corresponding to Boolean networks, synthesis of logic circuits is carried out in the design library of custom digital CMOS ASIC (Application-Specific Integrated Circuits made using complementary metal oxide semiconductor technology). In Boolean networks, node functions can be the logical operations “conjunction” or “disjunction” over literals of Boolean variables. A literal is a Boolean variable or its inversion. Minimization of BDD representations is carried out according to the number of Shannon decomposition formulas, minimization of Boolean networks – according to the number of literals in the formulas defining the networks.Results. The resulting logic circuits are compared in terms of chip area and speed (time delay). Experiments were carried out on 39 industrial circuit examples. The advantage (in 29 cases) of using the proposed subsystem extraction algorithms is shown compared to joint or separate minimization of the original system of Boolean functions, which is usually performed as the first stage of the synthesis of logic circuits.Conclusion. The new algorithms for subsystem extraction proposed in the paper have proven their effectiveness in the execution of various programs for optimizing multilevel representations of systems of Boolean functions. The developed software package allows improving the results of technologically independent optimization used in the implementation of digital system projects in custom digital CMOS ASIC.

Modular arithmetic is often used to create high-speed computing systems based on both custom digital VLSI circuits and field-programmable gate arrays (FPGAs). The problems of hardware implementation of neural networks based on modular arithmetic calculations are relevant today. In this study, the problem of implementing modular adders in the library for designing custom CMOS VLSI systems and FPGAs is considered. Systems of both fully and incompletely defined (partial) Boolean functions, as well as algorithmic descriptions in the VHDL language, are used as the initial descriptions of modular adders. Logical optimization preceding logical synthesis is carried out in the class of disjunctive normal forms, Reed–Muller polynomial representations, and representations of Boolean function systems by binary decision diagrams. Nine experiments are carried out on the efficiency of applying logic optimization in the circuit implementation of modular adders in the library for designing custom CMOS VLSI circuits and FPGAs. The obtained circuits of modular adders for CMOS VLSI systems are estimated by area (total number of transistors), delay, and power consumption; and for FPGAs, by the number of programmable logic elements and power consumption. The experimental results show that the use of partial function models and preliminary logical optimization based on binary decision diagrams makes it possible to obtain modular adders characterized by lower delay values. Algorithmic VHDL models make it possible to obtain CMOS modular adder circuits with a smaller area and lower power consumption.

Objectives. The problem of choosing the best methods and programs for circuit implementation as part of digital ASIC (Application-Specific Integrated Circuit) sparse systems of disjunctive normal forms (DNF) of completely defined Boolean functions is considered. For matrix forms of sparse DNF systems, the ternary matrix specifying elementary conjunctions contains a large proportion of undefined values corresponding to missing literals of Boolean input variables, and the Boolean matrix specifying the occurrences of conjunctions in DNF functions contains a large proportion of zero values.Methods. It is proposed to investigate various methods of technologically independent logical optimization performed at the first stage of logical synthesis: joint minimization of systems of functions in the DNF class, separate and joint minimization in classes of multilevel representations in the form of Boolean networks and BDD representations using mutually inverse cofactors, as well as the division of a system of functions into subsystems with a limited number of input variables and the method of block cover of DNF systems, focused on minimizing the total area of the blocks forming the cover.Results. When implementing sparse DNF systems of Boolean functions in ASIC, along with traditional methods of joint minimization of systems of functions in the DNF class, methods for optimizing multilevel representations of Boolean function systems based on Shannon expansions can be used for technologically independent optimization, while separate minimization and joint minimization of the entire system as a whole turn out to be less effective compared with block partitions and coatings of the DNF system and subsequent minimization of multilevel representations. Schemes obtained as a result of synthesis using minimized representations of Boolean networks often have a smaller area than schemes obtained using minimized BDD representations.Conclusion. For the design of digital ASIC, the effectiveness of combined approach is shown, when initially the block coverage programs of the DNF system is used, followed by the use of programs to minimize multilevel block representations in the form of Boolean networks minimized based on Shannon expansion.

Аннотация.В статье приводятся результаты экспериментальных исследований эффективности программ минимизации многоуровневых алгебраических представлений систем булевых функций, выполняемых при синтезе комбинационных схем.Результирующие минимизированные логические описания представлены в виде формул разложений Шеннона или формул, задающих булевы сети

A decisive influence on complexity and speed of a combinational logic circuit of library CMOS elements is exerted by the preliminary stage of technologically independent optimization of the implemented system of Boolean functions. At present, the main methods of such optimization in the logical synthesis of custom CMOS VLSI blocks are methods for minimizing binary decision diagrams — Binary Decision Diagrams (BDD) or their modifications. Graphical representations of BDD are built on the basis of the Shannon expansions of Boolean functions. A BDD graph corresponds to a set of interrelated Shannon expansion formulas that form a multilevel representation of the minimized system of Boolean functions. The efficiency of applying various optimization procedures of minimization for several types of BDD representations of systems of Boolean functions is investigated in the paper. 7hese procedures are used as a technologically independent optimization in the synthesis of multi-output logic circuits of library CMOS elements. In addition to single logical optimization procedures, sequences of such procedures are studied that form various methods of logical optimization of multilevel representations of systems of Boolean functions. The results of experiments on 49 examples of systems of Boolean functions are presented. 25 optimization routes have been studied, efficient routes have been determined for various types of specifications of function systems. The obtained experimental results are compared with the known ones. It has been established that to estimate the complexity of optimized algebraic representations of systems of functions, it is advisable to use such a criterion as the total number of literals (variables or their inversions) of Boolean variables.

Binary decision diagram (BDD) is used for technology-independent optimization, performed as the first stage in the synthesis of logic circuits in the design of application-specific integrated circuits (ASICs). BDD is an acyclic graph defining a Boolean function or a system of Boolean functions. Each vertex of this graph is associated with the complete or reduced Shannon expansion formula. Binary decision diagrams with mutually inverse subfunctions (cofactors) are considered. We have developed algorithms for finding algebraic representations of cofactors of the same BDD level in the form of a disjunction or conjunction of other inverse or non-inverse cofactors of the same BDD level. The algorithms allow reducing the number of literals by replacing the Shannon expansion formulas of a system of Boolean functions. It is proposed to use the developed algorithms for an additional logic optimization of the constructed BDD representations of systems of Boolean functions. The experimental results of application of the corresponding programs in synthesizing the logic circuits in the design library of custom VLSI CMOS circuits are presented.

The problems of synthesis of combinational circuits of code converters designed to reduce the length of words from a given set of encoded binary words is considered. The encoding assumes that different binary words will be encoded by different binary codes of shorter length. Code converters of this type are designed to reduce the length of binary words transmitted in digital systems over data buses when the bit depth of the transmitted words exceeds the bit depth of the data bus. For example, 18-bit or 17-bit words need to be transmitted over a 16-bit data bus. Each such word can be transmitted in two cycles of operation of a digital system; however, this approach reduces the overall performance of the system. One of the approaches to solve such problems is the development of combinational circuits that convert long binary encoded words into shorter ones. The proposed methods for solving the problem of synthesizing circuits of code converters are based on the compilation and logical minimization of such forms of systems of incompletely specified Boolean functions as disjunctive normal forms (DNFs) and binary decision diagrams called BDD representations. Using BDDs to minimize representations of k -valued functions that depend on Boolean variables is also proposed. Technology-independent logical minimization of functional descriptions of the designed code converters is proposed to be performed by programs for minimizing the systems of Boolean functions in the DNF class and programs for joint minimization of BDD representations of systems of completely specified Boolean functions. Minimization of functional descriptions is aimed at reducing the hardware complexity of combinational circuits in the basis of library elements or FPGA elements implementing code converters of the class in question.

Objectives . The problem of circuit implementation of incompletely specified (partial) k-valued logic functions given by tabular representations is considered. The stage of technologically independent optimization is studied to obtain minimized representations of systems of completely specified Boolean functions from tabular representations of partial functions of k-valued logic. According to these representations of Boolean functions, technological mapping is performed at the second stage of the synthesis of logic circuits. Methods . Using additional definitions of Multi-valued Decision Diagrams (MDD) representing partial functions of k-valued logic, and Binary Decision Diagrams (BDD) representing partial systems of Boolean functions at the stage of technologically independent optimization is proposed. The task of additional definition of MDD is oriented to reducing the number of vertices of the MDD graph that correspond to the cofactors of the Shannon expansion of a multi-valued function. Results . The MDD minimization problem is reduced to solving the problems of coloring undirected graphs of incompatibility of cofactors by minimum number of colors. Encoding of multi-valued values of arguments and values of functions of k-valued logic by binary codes leads to systems of partial Boolean functions, which are also further defined in order to minimize their multi-level BDD representations. Conclusion . The proposed approach makes it possible to define partial multi-valued functions to fully defined Boolean functions in two stages. At the second stage, well-known and effective methods are used to redefine BDD representing systems of partial Boolean functions. As a result of this two-step approach, minimized BDD representations of systems of completely defined functions are obtained. According to completely defined Boolean functions, a technological mapping into a given library of logical elements is performed, i.e. the optimized descriptions of Boolean function systems are covered with descriptions of logical elements

Objectives. Methods, algorithms and programs for solving problems of minimizing the DNF representations of Boolean functions are widely used in the design of digital systems to reduce the complexity (crystal area) of functional combinational blocks of digital systems placed into digital VLSI. The objective of the work is experimental comparison of domestic programs for minimizing Boolean functions in the DNF class included in the FLC-2 with two well-known foreign freely distributed programs for minimizing DNF known as Espresso IIC and ABC. Methods. Four sets sample of input data were used to compare the programs – there are widely known examples on which the effectiveness of the Espresso IIC program was tested and two sets of industrial examples from the practice of designing the logic circuits. Algorithms and programs for parallelization of calculations when separate functions of minimizing have been developed. Software tools for the application of joint minimization programs with separate minimization of functions are proposed. Results. The areas of preferred use and the execution time of programs for the source systems of functions (for minimization) characterized by large parameter values of dozens of arguments and functions, tens of thousands of elementary conjunctions are revealed. The efficiency of application of minimization programs for various forms of input data assignment is investigated – DNF, orthogonalized DNF, BDD (Binary Decision Diagrams) representations for systems of functions, truth tables and perfect DNF systems. Conclusion. The experimental results show the effectiveness of parallel programs – reducing the calculation time and increasing the dimensions of solved problems of separate minimization of Boolean function systems.

The paper describes the research results of application efficiency of minimization programs of functional descriptions of combinatorial logic blocks, which are included in digital devices projects that are implemented in FPGA. Programs are designed for shared and separated function minimization in a disjunctive normal form (DNF) class and minimization of multilevel representations of fully defined Boolean functions based on Shannon expansion with finding equal and inverse cofactors. The graphical form of such representations is widely known as binary decision diagrams (BDD). For technological mapping the program of "enlargement" of obtained Shannon expansion formulas was applied in a way that each of them depends on a limited number of k input variables and can be implemented on one LUT-k – a programmable unit of FPGA with k input variables. It is shown that a preliminary logic minimization, which is performed on the domestic programs, allows improving design results of foreign CAD systems such as Leonardo Spectrum (Mentor Graphics), ISE (Integrated System Environment) Design Suite and Vivado (Xilinx). The experiments were performed for FPGA families’ Virtex-II PRO, Virtex-5 and Artix-7 (Xilinx) on standard threads of industrial examples, which define both DNF systems of Boolean functions and systems represented as interconnected logical equations.

The lowering of power consumption in CMOS VLSI digital systems is one of the most important problems that appear now for developers of CAD systems. One of the effective approaches to lowering the dynamic power consumption is creation of an algorithmic description of the VHDL project, which provides for the deactivation of some functional blocks which are not necessary in particular moments. Contemporary synthesizers fulfill the high level synthesis of logic circuits by substitution of description of each VHDL construction with functionally structural description of a proper logic subcircuit. The results of digital logic circuit synthesis (the number of logic elements and power consumption) depend significantly on initial VHDL code. During initial VHDL code development it is possible to use different approaches to improve some parameters of synthesized logic circuit. At the algorithmic level of the digital design, it is necessary to provide for disconnection of the units, which cause the higher power consumption. In this paper such methods of algorithmic VHDL description of logic circuit are studied. The efficiency of the proposed methods is compared with the traditional method of VHDL-description which does not take the aspect of power con­sumption into account and is oriented only to the correct functionality of the developed logic circuit. To estimate the power consumption of logic circuits the approach is used which allows applying high-speed logical VHDL-simulation of structural descriptions (netlists) of logic circuits instead of slow SPICE simulation. The main conclusion of the provided study is the following: the clock gating and the storage of operand values for complex operations as well as zero value setting for simple ones are effective methods for the VHDL description of operational units with low power consumption implemented in the CMOS basis.

Аннотация-Описываются результаты экспериментального сравнения программ технологически независимой минимизации сложности многоуровневых представлений систем полностью определенных функций на основе разложения Шеннона.Графической формой таких представлений являются Binary Decision Diagrams (BDD) -диаграммы двоичного выбора.После получения минимизированных по числу вершин графов BDD, заданных в виде совокупности взаимосвязанных формул разложения Шеннона, выполняется синтез логических схем в одной и той же библиотеке проектирования заказных цифровых КМОП СБИС, результаты сравниваются по площади кристалла и по быстродействию (временной задержке).Дополнительного сокращения сложности логических описаний и улучшения результатов синтеза схем можно добиться во многих случаях

One of the directions of logical optimization of multilevel representations of systems of Boolean functions is the methods based on the search of subsystems of functions that have the same parts in the domains of functions of selected subsystems. Such subsystems are called related. The good relationship of functions leads to the appearance of a large number of identical structural parts (conjunctions, algebraic expressions, subfunctions, etc.) in optimized forms of representation of functions which are used in the construction of combinational logic circuits. The more the functions of the selected subsystem are related, the sooner it is expected that in the representations of the functions of this subsystem will be more identical subexpressions and synthesized logic circuits will have less complexity. We describe software-implemented algorithms for extracting subsystems of related functions from a BDD representation of a system of Boolean functions based on introduced numerical estimates of the relationship of BDD representations of functions. The relationship of Boolean functions is the presence of Boolean vectors, where the functions take the value as one, or of the same equations in BDD representations. BDD representations of Boolean functions are compact forms defining functions and are constructed as the result of Shannon decomposition of the functions of the original system (resulting from the decomposition of subfunctions) by all variables, which the functions of the original system depend on. The experiments show the effectiveness of proposed algorithms and programs in the synthesis of logic circuits from logic elements library.

The parallel automaton is considered which is the functional model of a discrete control device which allows taking into account the parallel character of logical control devices. The verification of parallel automata lies in testing all transitions in the graph of the complete states of automata and is conducted based on simulation. The software tools for constructing the compact tests for verifying the parallel automaton and for obtaining the VHDL model of parallel automata aimed at implementing their scheme are proposed. The obtained algorithmic VHDL models of the automata are synthesizable, which allows obtaining the scheme implementations of parallel automata in various design libraries.

Аннотация-Описывается система FLC-2, предназначенная для оптимизации иерархически организованных функциональных и структурных описаний логических схем, представленных на языке SF, являющемся внутренним языком системы.Для связи с другими САПР (системами автоматизированного проектирования) цифровых устройств в FLC-2 имеются средства конвертации SF-описаний в VHDL-описания (и обратно).Логическая оптимизация осуществляется на основе применения комбинированных методов, реализующих различные базовые оптимизационные приемы, -минимизацию систем булевых функций в классе ДНФ (дизъюнктивных нормальных форм), оптимизацию многоуровневых представлений систем булевых функций на основе булевых сетей и BDD-представлений, поляризации и декомпозиции матричных и скобочных форм, выделения подсистем функций, связанных по областям определения.В системе FLC-2 реализован продукционный подход для управления последовательностями проектных процедур, предназначенных для их использования на этапе логического проектирования сложных функциональных блоков заказных цифровых СБИС (сверхбольших интегральных схем).Эксперименты показали целесообразность использования программ системы FLC-2 для пред