Comprehensible neural network explanations are foundations for a better understanding of decisions, especially when the input data are infused with malicious perturbations. Existing solutions generally mitigate the impact of perturbations through adversarial training, yet they fail to generate comprehensible explanations under unknown perturbations. To address this challenge, we propose AGAIN, a factor graph-based interpretable neural network, which is capable of generating comprehensible explanations under unknown perturbations. Instead of retraining like previous solutions, the proposed AGAIN directly integrates logical rules by which logical errors in explanations are identified and rectified during inference. Specifically, we construct the factor graph to express logical rules between explanations and categories. By treating logical rules as exogenous knowledge, AGAIN can identify incomprehensible explanations that violate real-world logic. Furthermore, we propose an interactive intervention switch strategy rectifying explanations based on the logical guidance from the factor graph without learning perturbations, which overcomes the inherent limitation of adversarial training-based methods in defending only against known perturbations. Additionally, we theoretically demonstrate the effectiveness of employing factor graph by proving that the comprehensibility of explanations is strongly correlated with factor graph. Extensive experiments are conducted on three datasets and experimental results illustrate the superior performance of AGAIN compared to state-of-the-art baselines.

In the realm of interpreting Graph Neural Networks (GNNs), concept-based interpretability stands out for its ability to recognize diverse subgraph structures as semantic concepts, elucidating GNN predictions. While existing methods in this domain have shown promise in enhancing human understanding, they often fall short in ensuring the completeness of the concept set. These interpreters may lack essential concepts, impacting interpretation accuracy. The root of this issue lies in the absence of the Markov assumption between the set of concepts and predictions, resulting in non-zero mutual information between input features outside the concept set and GNN predictions. To address this, a novel concept self-expansion method, GENII, is introduced. GENII employs a side-channel to learn potential concepts and known concepts crucial for accurate predictions, bypassing the Markov assumptions and enhancing conceptual completeness.

The wide application of Ethereum smart contracts in the Internet of Things, finance, medical, and other fields is associated with security challenges. Traditional detection methods detect vulnerabilities by stacking hard rules, which are associated with the bottleneck of a high false-positive rate and low detection efficiency. To make up for the shortcomings of traditional methods, existing deep learning methods improve model performance by combining multiple models, resulting in complex structures. From the perspective of optimizing the model feature space, this study proposes a vulnerability detection scheme for Ethereum smart contracts based on metric learning and a bidirectional long short-term memory (BiLSTM) network. First, the source code of the Ethereum contract is preprocessed, and the word vector representation is used to extract features. Secondly, the representation is combined with metric learning and the BiLSTM model to optimize the feature space and realize the cohesion of similar contracts and the discreteness of heterogeneous contracts, improving the detection accuracy. In addition, an attention mechanism is introduced to screen key vulnerability features to enhance detection observability. The proposed method was evaluated on a large-scale dataset containing four types of vulnerabilities: arithmetic vulnerabilities, reentrancy vulnerabilities, unchecked calls, and inconsistent access controls. The results show that the proposed scheme exhibits excellent detection performance. The accuracy rates reached 88.31%, 93.25%, 91.85%, and 90.59%, respectively.

Instability at transient frequency caused by faults in complex power systems is one of the greatest threats to operational safety. By analyzing the frequency response of power system in real-time and adopting control strategies promptly, power system accidents can be efficiently prevented. While existing online analysis methods integrate physical-driven and data-driven methodologies, they do not effectively utilize frequency timing characteristics. Consequently, a swarm intelligence fusion model, which integrates physical-driven and data-driven methods, is proposed as an improved frequency response analysis method. The transient frequency affecting components are separated into primary state variables and system time series data based on the properties of the time sequence. To preserve the actual relationship of the electrical mechanism model, the system frequency response (SFR) model is used as the physical-driven method for the primary state variables of the system. The Long Short Term Memory (LSTM) network was used as the data-driven method to extract timing features and correct the SFR model’s prediction using the system time series data as input. The two methods are combined using the bootstrap mode to form the fusion model, and the structure of the model is optimized using an improved sparrow search algorithm (ISSA), a swarm intelligence optimization algorithm. The model structure is adapted autonomously, implementing a method for online frequency response analysis. The simulation on the New England 39-bus system has verified that the method can quickly and accurately calculate the dynamic process of frequency response after a large-scale disturbance.

Spatial architecture has emerged as a promising way to accelerate artificial neural networks (ANNs), but requires to model the ANN hardware dataflow to obtain the optimal dataflow choice to obtain ideal acceleration performance. Recently, many modeling methods exploit imperative instructions to depict ANN dataflow, but these methods lack the representation for the temporal and spatial migration of dataflow in spatial architecture, which leads to inaccurate metrics estimation. To address the above challenges, TESDAM is proposed as an ANN dataflow modeling framework based on spatiotemporal migration representation. TESDAM designs a spatiotemporal migration matrix and a PE adjacency matrix to depict loop instance mapping, tensor mapping, spatiotemporal migration path, and hardware PE interconnection. Moreover, a comprehensive dataflow metrics model is supported by TESDAM to evaluate PE utilization, latency, and data reuse. Expensive experiences demonstrate that TESDAM reduces the overhead by 23.83

区块链是具有去中心化、防篡改属性的分布式数据库,但由于区块链共同监管和高透明度的特点,也导致用户的隐私数据被公开泄露,从而使用户的隐私信息安全得不到保障.因此,隐私保护问题成为区块链数据安全研究的重点和难点.近年来,基于零知识证明技术的许多区块链隐私保护方案被提出,现存的解决方案虽已得到应用,但针对不同的应用场景仍存在着诸多缺点.本文对现有的基于零知识证明的区块链隐私保护技术进行了深入分析与比较,并对目前的保护方案进行阐述与总结,最后针对现有的区块链隐私保护方案存在的问题,提出未来可研究的重点,期望能够为区块链隐私保护的研究工作指明研究方向,并奠定坚实的工作基础.

The decentralization of blockchain can easily lead to the leakage of users’ private data at the transaction layer,which in turn leads to information security issues.The zero-knowledge range proof is designed to confidentially verify that the transaction data belongs to a legal positive integer range without revealing the transaction data.It effectively solves the problem of blockchain privacy leakage.The existing blockchain range proof scheme can still be further optimized in terms of proof speed,verification speed and calculation cost.In addition,the existing solutions cannot handle the floating-point number problem,thus limiting the application fields of range proofs.This paper proposes an efficient range proof scheme with constant computational cost and universal for floating-point numbers and integers,ZKFERP.It improves the zero-knowledge protocol based on Bulletproofs to optimize the proof structure,and a Lagrangian inner product vector generation method is designed to make the witness generation time constant and the commitment is constructed according to the floating-point number range relationship to implement floating-point range proof.ZKFERP only relies on the discrete logarithm assumption,and third-party credibility is not required.The communication cost and time complexity of ZKFERP are constant.Experimental results show that,compared with the most advanced known range proof scheme,ZKFERP’s proof speed is increased by 40.0%,and the verification speed is increased by 29.8%.

异构计算作为一种特殊的并行计算方式,能根据计算任务的特点发挥不同计算资源的能力,在提高服务器计算性能、能效比和实时性方面有极大优势,但目前异构计算环境存在编程复杂、可信性无法保证的问题.针对以上问题,提出了一个基于状态变迁矩阵(STM)的编程框架,可以集成GPU和FP-GA的资源.通过状态迁移矩阵对CUDA和Vivado的应用程序接口(API)进行集成,自动生成异构计算所需要的标准C代码.通过PCIe总线连接GPU和FPGA设备,从而可以在这些异构计算单元之间进行数据传输,中间无需使用系统CPU内存.并且通过GPUDirect RDM A实现了FPGA作为主控器的PCIe通信,突破了GPU作为主控器的PCIe通信当中读取操作的短板.实验表明,相比共享内存的通信方式,FPGA作为主控器的PCIe通信方式的通信效率提高了1.4倍,实现的数据速率接近理论带宽的最大值.

为测试国产数据库和各大厂商数据库处理数据性能以便设计人员选择合适的大数据管理系统,设计了一款基于TPC-DS测试标准的数据库处理性能测试软件TPC-DS_Utensil.通过分析TPC-DS测试标准设计了加载(Load)测试、 功率(Power)测试和吞吐量(Throughput)测试三大核心功能;为了方便设计人员对测试过程进行监控与分析设计了查询验证、 性能计算和日志管理等辅助功能.通过对MySQL、Oracle、Hive和Hbase进行性能测试,表明该测试工具能够准确地反映服务器性能.

The traditional system design method cannot guarantee the dependence of large-scale and complex real-time embedded software. The model constructed by UML and other semi-structured modeling languages does not support simulation and verification, nor can it find requirements omission and logic contradiction. The Extended Hierarchical State transition Matrix model (EHSTM) which supports hierarchical modeling and concurrent States is proposed. The formal modeling of large-scale software system is simplified by model hierarchy. All relations between any two complex system concepts are clarified by hierarchical States and state parallelization, and the parallel behavior modeling of system is supported at the same time. After the model is constructed, it can be simulated and verified by a bounded model verification tool "GarakabuII". C source codes can be generated automatically after model checking and verification. In this way, system developers can focus only model design, which simplifies the system design process. Finally, a system design tool ZIPC based on EHSTM model is designed. Aiming at the problems of atomicity violation and data race in concurrent program development, ZIPC tool is used to construct the model, and the above problems can be effectively solved by experimental verification.

Schedulability analysis is a very important part in real-time system research. Because the scenarios faced by real-time systems are very complicated, the functional characteristics must be combined with the predictability of response time. It is necessary to ensure the correctness of the calculation results and meet the real-time requirements. To solve this problem, we propose the IEDF (Improved Earliest Deadline First) algorithm, which is combined with the queuing theory model. The IEDF algorithm is based on the EDF (Earliest Deadline First) algorithm, which is more suitable for the scheduling of real-time embedded system. Scheduling of non-periodic tasks that arrive randomly. There are two types of tasks in the task set, tasks with a high static priority are executed first. In the ready queue of the same priority task, the deadline and execution time are considered. The comparison of simulation experiments shows that: the sum of waiting time in the execution of IEDF with enough deadline is much less than that of ordinary queuing algorithm; the number of errors in the execution of IEDF algorithm with deadline is much less than that of ordinary queuing algorithm. These results demonstrate the feasibility of the IEDF algorithm.

. Software requirement analysis and design documentation are important basis for software development. The documentation quality does directly affect the quality of software development in the subsequent stage. At present, the requirement analysis and design documents are described by a natural language. These documents are usually reviewed by the document walk-through method. The illegibility and ambiguity of the text expression may cause problems such as missing requirements and logical contradictions. This paper introduces the advantages and modeling process of formalized modeling method -- State Transition Matrix (STM) in detail, and proposes to use the Extended State Transition Matrix (ESTM) formalized method to model the requirements analysis and system design documents. According to the transition feature performs symbolic coding and formal description of the properties, the missing requirements and logical contradictions would be discovered in the design document, test cases and testing code could also be generated. The experimental part takes the train control system test as an example, utilized the formal verification method, judged whether there are logic errors in the document. The result shows that the method can better solve a part of logic problems and requirement vulnerabilities that cannot be found by the traditional code test method

This paper proposed an interrupt handler with a time slice, which is enabled to complete the executing sections of low priority interrupt within the time period of the time slice. This method could not only reduce the numbers of interrupt threads rotations but also save the space to record the interruption scene for interrupt execution. The experimental part used the two types of interrupt handlers by the ordinary queuing model and inserting time slices consecutively, to simulate two-priority interrupt processing in a system. The comparison of simulation experiments shows that: the interrupt handler with time slices could obviously reduce the rotation number of interrupt handling thread switched, thereby saving the space for the interruption of site preservation and providing a reference for further research on the interruption of embedded systems.

Heterogeneous computing, as a kind of special parallel computing method, can exert the ability of different computing resources based on the characteristics of computing tasks and is much advantageous in improving server computing performance, energy efficiency ratio (EER) and real time performance. FPGA-GPU-CPU heterogeneous computing was born for the real-time processing of massive of data. However, the communication bottlenecks between different computing units have set restrictions on the computing capabilities of heterogeneous platform. In view of the above issues, this article connects GPU and FPGA devices through the PCI Express bus, so that data can be transmitted between these heterogeneous computing units without the assistance of the system CPU memory. And, we have realized that the PCIe communication by taking FPGA as the main controller through GPUDirect RDMA, which improves the weakness of slow reading in PCle communication where the GPU as the main controller. Experiments show that we have improved the efficiency by 1.4 times compared to the memory sharing-based communication and the data rate has been made closest to the maximum theoretical bandwidth.

嵌入式并发软件的中断嵌套和线程交织等程序的随机性和不确定性(Randomicity and Nondeterminism)会引起数据竞争(Data Race)和原子性违背(Atomicity Violations)等并发缺陷问题,并且这些问题很难被修复和重新构建.针对嵌入式软件中的数据竞争和原子性违背这类并发缺陷问题,文中提出了瘦中断处理(Thin Interrupt Service Routine,Thin ISR)方式.首先,利用状态迁移矩阵(State Transition Matrix,STM)进行建模,把中断处理程序中与访问共享变量相关的程序段移植到主程序中,即中断处理程序只负责将外界中断请求数据存到缓冲区中,中断的具体处理由主程序完成;然后,利用构建的STM模型生成对应的C代码,这样可以有效地避免原子性违背和数据竞争等并发缺陷;最后,利用排队方法对中断的到达时间与离开时间进行仿真.实验结果验证了本方法在解决数据竞争和原子性违背等并发缺陷问题方面的可行性与有效性.

The real-time interaction between embedded software and its external environment is conducted through the interrupt mechanism. Since the interrupt request is random and responds according to priority, the execution of embedded software is non-sequential, which leads to the non-deterministic software behaviors. If these non-deterministic behaviors can be quantitatively pre-analyzed during the software design phase, the reliability of embedded software can be improved effectively. In this paper, we first provide an embedded software behavior model based on extended deterministic and stochastic Petri nets (EDSPN). Through EDSPN, the interrupt behavior of embedded software can be effectively modeled. Then we put forward a probabilistic model checking method of Continuous Stochastic Logic (CSL) for EDSPN to analyze embedded software behavior. For alleviating the state explosion problem, the above method uses the bounded model checking (BMC) technique. We present the model checking methods and the probability metric calculation methods for CSL operators under bounded semantics. Finally, by analyzing the EDSPN model of embedded software with multiple interrupts, we compare the analytical capabilities of BMC method and non-BMC method. The experiment shows that when the state space of EDSPN is large and is hard to calculate, the bounded checking algorithm can be used to approximate the software behavior. The conclusions obtained are helpful to understand the properties to be verified.

在实时嵌入式系统设计中,为了保证系统的安全运行,需要验证系统是否满足时限,即任务必须在截止期之前完成,否则实时系统将失败.目前衡量实时嵌入式系统实时性的重要指标是任务的最坏情况执行时间(Worst Case Execution Time,WCET).文章首先综述了WCET分析以及研究WCET分析的主要方法.分析了在当前多核平台上、复杂处理器架构下WCET分析存在的主要问题,并根据当前WCET分析存在的问题展开讨论,分别针对时序分析、微系统结构分析和多核多任务调度策略等方面分析了国内外的研究进展.最后提出了一种基于深度学习的自适应实时DVFS算法,该算法可以进行动态电压和频率调节(DVFS),以达到节能的目的;同时还能够动态修正程序的WCET值,为未来嵌入式系统中的WCET分析与预测提供指导方法.

大型软件的调试往往需要花费大量人力和时间,因此自动化的软件故障定位方法成为更好的选择.现有故障定位方法大都基于用例的覆盖信息进行分析,没有完全考虑测试用例执行时的顺序信息.针对上述问题,提出测试用例执行轨迹分析的故障定位方法,该方法首先通过控制流分析获得测试用例的执行轨迹,然后将执行轨迹编码成序列信息用于训练循环神经网络,最后将一组虚拟测试用例输入网络中预测代码块的可疑度.通过在Siemens套件上的实验和分析,验证了所提方法的有效性.

The rapid increase in the scale and complexity of the circuit system has led to serious problems in safety and reliability. Therefore, fault tolerance was proposed. Fault location as part of fault tolerance is indispensable. However, fault location methods are mostly limited to small data volume and high system complexity. How to achieve the fault location of the circuit system has always been a focus question. This paper proposes a Hierarchical Multi-module Fault Location Mechanism (HMFLM). Cartesian Genetic Programming (CGP) is exploited to generate circuits and random injects faults into it. The model matching library is used to store the training model of the layering module circuit and detect circuit faults in real time. The recovery priority of the fault circuits utilize Fault Analysis Tree (FAT) to determine, therefore, we can effectively facilitate fault recovery. The results show HMFLM can effectively locate multiple faults and improves the real-time and reliability of fault diagnosis.

The self-repairing feature of evolution hardware can effectively recover repairable faults of circuit systems.Due to the slow rate and low success rate in circuit evolution process, how to accomplish the evolution within the time constraint becomes a major challenge.We propose a real-time faulttolerant system based on evolution hardware, in which fault analysis trees are used to monitor circuit faults in real time, a fault compensation mechanism to maintain the normal operation of the system, and the evolution hardware technique is adopted to repair circuit faults so as to realize online real-time repair of faults.We test the fault-tolerant system on FPGA through random fault injection.Several evolutionary algorithms are used to verify the self-repairing capability of the fault-tolerant system.The results show that the repair rate of the fault circuit can reach 95％under the real-time constraint and the stability and reliability of the system are improved.