The emergence of new instruction set architectures (ISAs) poses challenges in ensuring compatibility with legacy applications. Dynamic binary translation (DBT) serves as a crucial approach for achieving cross-ISA compatibility, enabling legacy applications to run compatibly with cross-ISAs. However, software-based translation encounters significant performance overhead, including substantial memory access and insufficient exploitation of target architecture features. The significant performance overhead challenges hinder the practical implementation of DBT. In this paper, we investigate a novel peephole optimization approach. First, we perform peephole analysis to identify redundant memory access and suboptimal instruction sequences. Next, we leverage live variable analysis to eliminate redundant memory-access instructions. Additionally, we bridge the gaps between cross-ISAs by exploiting ISA-specific features through instruction fusion. Finally, we implement the proposed optimization design using the open-source QEMU and extensively evaluate it on both ARM64 and SW64 platforms. The experimental results reveal that SPEC2006 benchmark effectively gets a maximum performance speedup of 1.52×, alongside a reduction in code size of up to 13.98%. These results affirm the effectiveness of our optimization approach in DBT performance and code sizes.

Dynamic binary translation (DBT) is a core technology that enables the migration of legacy software to different instruction set architectures while maintaining the original semantics. However, the development and maintenance of an efficient cross-DBT system are challenging. Key challenges include memory access overhead, inefficient instruction simulation, and frequent context switches. In this paper, we propose three novel optimization techniques. First, we formalize a register mapping cost model and investigate a hierarchical register mapping approach to bridge the memory access overhead. Second, we accelerate floating point (FP) emulation by surrounding the use of hardware FP unit with high-efficiency non-FP code. Third, we present a function inlining approach to alleviating the overhead associated with indirect control lookup. On the system side, we implement our approach on ARM64 and SW64 architectures based on QEMU and extensively evaluate the effectiveness with the SPEC2006 benchmark suite. The experimental results show that an average of 1.28× performance speedup and 13.41% code size reduction can be achieved on SW64. Similarly, on ARM64, we achieve an average of 1.15× performance speedup and 11.48% code size reduction.

Manycore has become the mainstream processor architecture for building HPC supercomputer systems,providing powerful computing power for High Performance Computing(HPC)exascale supercomputers.With the increasing number of cores integrated on manycore processor chips,the competition for large-scale cores for memory resources has become more intense.Manycore on-chip memory hierarchy is an important structure that alleviates the"memory wall"problem,aids HPC applications better play the computing advantages of manycore processors,and improves the performance of practical applications.The design has a significant impact on the performance,power consumption,and area of an on-chip system.The design of a many-call on-chip memory hierarchy has a significant impact on the performance,power consumption,and area of manycore systems.It is an important part of the structural design of manycore systems and is a research interest in the industry.Owing to the differences in the development history of manycore chips,the design technology of on-chip microarchitecture,and the different requirements of the application fields,the current HPC mainstream manycore on-chip storage hierarchy is different;however,from the perspective of horizontal comparison and the vertical development trend of each processor,as well as from the changes in application requirements brought by the continuous integration and development of HPC,data science,and machine learning,the hybrid structure of the SPM+Cache would most likely become the mainstream choice for the on-chip storage hierarchy designs of manycore processors in HPC exascale supercomputer systems in the future.For exascale computing software and algorithms,the designs and optimization based on the characteristics of the manycore memory hierarchy can aid HPC applications benefit from the computing advantages of manycore processors,thus effectively improving the performance of practical applications.Therefore,software,algorithm design,and optimization technology for the characteristics of the manycore on-chip storage hierarchy is also a research interest in the industry.This study first partitioned the on-chip memory hierarchy into multilevel Cache,SPM,and SPM+Cache hybrid structures according to different organizations,and then summarized and analyzed the advantages and disadvantages of these structures.This study analyzed the current status and development trend of the memory hierarchy designs of the chips of mainstream exascale supercomputer systems,such as the international mainstream GPU,homogeneous manycore,and domestic manycore.In summary,the research status of software and hardware technologies is related to the design and optimization of the memory hierarchy from the manycore of the manycore LLC management and cache consistency protocol,SPM management and data movement optimization,and the global perspective optimization of the SPM+cache hybrid architecture.Thus,this study looks forward to the future research direction of on-chip memory hierarchy based on different perspectives,such as hardware,software,and algorithm designs.

Alltoall is an important collective communication mode that is widely used in scientific and engineering computing applications. In applications such as FFT, using as much memory space as possible can improve applications’ efficiency and expand the scale of problems to be solved. High-bandwidth alltoall_inplace communication under space-constrained buffer conditions can significantly improve the performance of such applications. In this paper, two alltoall_inpalce communication algorithms under the condition of limited buffer space are designed for the domestic parallel computing system based on Sunway many-core processor. The alltoall_inpalce communication interfaces for both the core array and the whole CPU node are realized. The experimental results show that algorithms implemented in this paper can achieve high bandwidth using limited buffer space.

高性能计算中,硬件支持的多播操作对应用程序性能具有至关重要的影响.Infiniband网络中现有的两类多播路由算法中,MINIHOP-MC未考虑路由均衡性问题,导致链路edge forwarding index(EFI)指数很大,严重影响多播消息性能;SSSP-MC虽然部分考虑了路由均衡性问题,但其运行时间很长,不能满足超大规模互连网络的需求.提出一种负载均衡的快速多播路由算法FULB-MC,可用于存在大量多播组的超大规模互连网络环境.该算法采用自底向上的多播树构建方法,并综合利用两种负载均衡策略根据局部负载信息进行多播路由选择.还提出了新的加入/离开多播组机制,避免频繁计算多播路由问题.在各种拓扑结构、各种通信模式下对FULB-MC进行了大量测试.结果表明,在运行时间方面,FULB-MC显著低于SSSP-MC;在链路EFI指数方面,FULB-MC明显优于MINIHOP-MC,而与SSSP-MC基本相当.

Using in-network-computation capabilities of the network devices (also called hardware collectives) to optimize MPI collectives has become popular in high-performance computing, and shows significant performance advantages. However, the hardware collectives are not flawless in practical use scenarios. One of the problems is that it is difficult to use. In order to obtain the performance advantage of hardware collectives, the network management software need to create dedicated aggregate tree for each MPI communicator, which is a complicated task. One solution is to make MPI communicators sharing the global imprecise aggregate trees created by the management software when initiating networks, but it leads to heavy interference between MPI communicators and causes significant performance degradation. So we have to make tradeoff between performance and ease of use. We propose a hybrid approach to optimize MPI collectives by in-network-computation and point-to-point messages. On the one hand, we use the pre-created aggregate trees in each super-node, rather than sending requests to the network management software to create dedicated aggregate trees. On the other hand, the hardware collectives are transferred only in the local super-node, so it cannot disturb the jobs running on other super-nodes. We provide a cost model to evaluate the overhead of the hybrid collective algorithms. We also test its performance in the new generation Sunway supercomputer. The results show that our approach reduces the median latency by 18%~74% compared to collectives implemented by point-to-point messages, although the performance decrease slightly compared to the original hardware collectives. In addition, the tail latency of our approach is significantly lower than that of the original hardware collectives in the presence of heavy interference.

在高性能计算领域,多播路由算法对硬件集合操作的性能具有至关重要的影响.随着系统规模的不断扩大,多播组的个数急剧增加,可能会超过硬件支持的多播表条目数,而现有的多播路由算法要么没有给出解决方案,要么存在时间开销大、多播路由经常变化等问题.为此,首先对胖树中的无冲突多播生成树数量进行了量化研究,并以此为基础提出了一种适用于胖树的高效实用的定制多播路由算法(customized multicast routing for limited multicast forwarding table size,C-MR4LMS).C-MR4LMS在构建多播树时,根据多播组的 MGID(multicast global identification)静态地将多播组映射到1棵生成树中,从而快速完成多播树的构建;而在合并多播树时,仅需合并使用同一生成树的多播组,且不会改变被合并多播组的路由.然后提出了 2种减少多播树冲突的方法:一是分层的MGID分配策略,以避免出现同一终端节点使用同一颜色加入多个多播组的情况;二是相互无干扰的作业节点分配策略,保证2个作业的多播组互不干扰.最后,在ibsim模拟器及神威E级原型机上对C-MR4LMS进行了测试,该多播路由算法计算多播路由的时间比现有的多播路由算法有了显著下降,最大下降了 94％.

Operator acceleration libraries based on different hardware devices have become an indispensable part of deep learning framework,which can provide performance improvement for large-scale training or inference tasks dramatically.The current main-stream operator libraries are all developed based on GPU architecture,which is not compatible with other heterogeneous designs.SWDNN operator library is based on the development of SW26010 processor,which can not give full play to the performance of the upgraded SW26010 pro processor,nor can it meet the needs of the current large neural network models such as GPT-3 for large memory capacity and high memory access bandwidth.According to the architecture characteristics of SW26010 pro processor and the training requirements of large neural network model,a three-level parallel and neural network operator task sche-duling scheme based on multi-core group is proposed,which can satisfy the memory requirements of large model training and improve the overall computing performance and parallel efficiency.A memory access optimization method with triple asynchronous flow and overlap of computation and memory access is proposed,which significantly alleviates the memory access performance bottleneck of neural network operators.Based on the above methods,this paper constructs the SWTensor many-core group operator acceleration library based on the SW26010 pro processor.The experimental results of natural language processing model GPT-2 show that,computation-intensive operators and memory access intensive operators in SWTensor operator library reach the maxi-mum of 90.4% and 88.7% of the theoretical peak values respectively in single-precision floating-point computing performance and memory access bandwidth.

高性能计算中,硬件支持的多播操作对集合通信的性能具有重要影响.随着超级计算机系统规模的不断扩大,多播组的个数急剧增加,可能会超过硬件支持的多播表条目数,而现有的多播路由算法没有给出相应的解决方案.提出一种面向有限多播表条目数的多播路由算法MR4LMS(multicast routing for limited MFT size),该算法使用先构造后染色、先染色后构造2种多播树构建方法,可显著降低所需的多播表条目数;而在多播表条目数不足时,通过合并算法将多个相似的多播组合并到一起以进一步减少所需的多播表条目数.在多种典型拓扑结构及通信模式下对MR4LMS进行了测试,结果表明仅需设置256个多播表条目就能够支持数千甚至数万个多播组,满足典型应用的需求.还对多播路由算法的最大EFI(edge forwarding index)及运行时间进行了测试,获得了令人满意的结果,表明MR4LMS可用于超大规模互连网络.

As an effective solution for hiding memory access latency, data prefetching, including hardware prefetching and software prefetching, is widely used to alleviate "memory wall" problem. Current software prefetching typically prefetches data to L1 cache. However, this strategy suffers from issues like inaccurate timeliness and over prefetch. To address this issue, we propose CSPM, a coordinated software prefetching mechanism for multi-level caches. To further improve memory performance, CSPM inserts prefetch instructions to multi cache levels according to access pattern and cache utilization, instead of only inserting prefetch instructions to L1 Cache. In this way, CSPM allows coordinately prefetch data to different cache levels. We implement CSPM based on the software prefetching framework in the GCC compiler, and uses STREAM and SPECfp 2006 benchmark suites to evaluate the effectiveness of CSPM. Results show that, compared to only prefetching data to L1 cache, CSPM delivers an average speedup of 1.37x, 2.49x, and 1.04x for STREAM under single core, STREAM under multiple cores, and SPECfp2006, respectively.

Performance tuning faces challenges of the heterogeneousness, complexity and flexibility of the modern processors. Due to the limited knowledge of the underlining architecture, users are usually confused about which optimizing should be enabled to speed up their applications on the target processor. In this paper, a configurable tuning framework, CTFS, is proposed to probe the compiler options automatically to optimize programs on SHENWEI system. Tightly coupling with the system software of the SHENWEI family processors, CTFS provides flexible iterative target supports and configurable iterative progress, which dramatically improvement user-friendliness of the computer systems built on SHENWEI family processors. The evaluation shows that with the help of CTFS, the performance of the SWDNN cases can be improved about 9% on average compared with the -O3 optimizing level. A case study of a real-world application, Graph500, which is speeded up by 27% with the help of CTFS.

In recent years, the improvements of system performance and energy efficiency for supercomputers have faced increasing challenges, which create more intensive demands on the architecture design for realizing exascale computing. This paper first analyzes the main requirements of exascale computing on the aspects of the parallel computing application and supercomputing center operation. Afterwards, a mapping scheme of “demands-challenges-architecture” is proposed. Then, the major challenges of exascale supercomputer, such as scalability, power consumption, data movement, programming and availability, are thoroughly analyzed, and the corresponding appropriate solutions are proposed. Moreover, this paper proposes the Sunway computer architecture towards exascale computing in which the many-core processor, network chipset and software system are all domestically-designed. The technology roadmap of Sunway supercomputer will hold the comprehensive design methods for the architecture, including the processor, interconnect network, assembly structure, power supply, cooling system, system software, parallel algorithm and application support, promising great advances for exascale supercomputing.

As we all known, power constraint is the biggest challenge to build an exascale computing system. Among all parts of high performance processor, on-chip memory, including register, cache and so on, is accessed frequently and incurs high power consumption during program executing. Due to trivial overhead and good portability, compiling is a promising way to reduce power consumption and thermal dissipation of processor. In this paper, we focus on compiling to save power of on-chip memory access. A compiler optimizing on bypassing registers is proposed to reduce the number of register access in order to lower the power of the register files. Besides that, to save the power consumption of cache, another compiler optimizing is proposed to elegantly adjust loop transformation to make a better use of L0 cache. Finally, in order to evaluate the effectiveness of the above techniques, we build a systematic evaluation platform, named as GEAT, which consists of compiler, performance simulator and power simulator. Experiment results show that our proposed techniques can effectively reduce the power consumption of on-chip memory with trivial overhead of performance.

针对超级计算机系统中网络引导时间开销大的问题,提出网络引导分布算法是影响网络引导性能的主要因素之一,是优化网络引导性能的主要方向的观点.首先,分析了影响大规模网络引导性能的主要因素;其次,结合一种典型超级计算机系统,分析了超节点循环分布算法(SCDA)和插件循环分布算法(BCDA)的网络引导数据流拓扑结构;最后,量化分析了这两种算法对各个网络路径段的压力和可获得的网络性能,发现BCDA性能是SCDA性能的1～20倍.通过理论分析和模型推导发现,在计算节点和引导服务器之间使用更细粒度的映射算法可以在引导部分资源时使用尽量多的引导服务器,减少对局部网络资源的过早竞争,提升网络引导性能.

大规模异构众核计算机系统具有计算能力强、性能功耗比高等突出优点,已成为超级计算机的发展方向,但其复杂的异构结构和庞大的系统规模,也使系统的可用性面临巨大挑战,因此研究面向大规模异构众核系统的轻量级容错技术具有重要意义.针对传统基于检查点的系统级容错开销过大的问题,在Parallel C语言中设计并实现了故障局部感知的轻量级降级、编译指导与自动分析的检查点等语言支持的容错机制,兼顾了好用性和高效性.局部故障感知的轻量级降级结合动态任务调度框架实现,支持众核系统,可扩展到百万以上并行规模;编译指导与自动分析的检查点通过程序员插入简单的编译指示,由编译器进行分析,提示不需要保留的数据,可有效降低保留恢复的数据量.神威太湖之光超级计算机上的测试数据表明,两种容错措施相对于传统容错方法效果良好,轻量级降级的容错开销小于1％,相对于传统回卷容错方法单次故障执行时间可减少3.5％以上,编译指导与自动分析的检查点在典型应用中最多可将保留量降低至1/10,具有很好的实用性.

Hadoop is a popular distributed framework for massive data processing. HDFS is the underlying file system of Hadoop. More and more companies use Hadoop as data processing platform. Once Hadoop crashes, the data stored in HDFS can not be accessed directly. We present HDUMP, a light-weight bypassing file system, which aims to recover the data stored in HDFS when Hadoop crashes.

Squire Kilometre Array (SKA) project generates almost the hugest data volume in the world. SKA data flow pipelines need almost real-time processing ability, which brings huge challenges to the execution frameworks (EF for short). We propose a cost model for a typical SKA data flow pipeline named as MID1 ICAL pipeline on Spark. By simulating the I/O of MID1 ICAL pipeline with a reduced SKA data, we evaluate several different implementations of MID1 ICAL pipeline and conclude the optimized method for this pipeline on Spark.

Heterogeneous many-core architecture,with ultra-high performance to power consumption ratio,has become an important trend of supercomputer architecture development.However,many-core systems always have more complex parallel hierarchy and memory hierarchy,hence posing a great challenge to programming and optimization.Therefore,the study of many-core-oriented parallel programming techniques is of great significance,since it can reduce the difficulty of parallel programming on domestic many-core systems and improve the performance of parallel programs.This work proposes a multi-model parallel programming model upon unified architecture,including heterogeneous-fused speedup programming model and isomorphic independent programming model.Based on this model,Parallel C programming language is designed to effectively describe heterogeneous parallelism of the domestic many-core system.Compared to MPI+X programming pattern,programming with Parallel C has a global perspective,as well as advantages in the hierarchy locality description,one-side message passing and multi-core applications compatibility.The Parallel C compiler system constructed with Open64 fully supports the heterogeneous-fused speedup programming model and isomorphic independent programming model.In addition,the design and implementation of data layout and automatic DMA optimization,compiler-directed thread proxy optimization and topology-aware collective communications optimization are presented.The performance of the proposed method is evaluated with the Miro Benchmark and practical applications on Sunway Taihu Light computer system.Experimental results show that Parallel C language and the compile system have good performance and scalability to effectively support large-scale applications.

引言 科学计算、理论研究和科学实验,一直被认为是研究世界的三大技术手段. 随着计算技术的发展,科学计算对超级计算机能力的要求越来越高.因为高性能计算是解决我国经济建设、科技进步、国家安全等一系列重大问题不可替代的重要手段. 在过去的15年里,我国通过部署多种国家级科技项目和资助计划,来推动我国高性能计算能力的提升,也成功研制多台超级计算机,逐步形成了具有一定规模的国家级高性能计算服务环境,支撑了一批重大领域应用.国家863计划支持的“神威”、“天河”、“曙光”等超级计算机现已进入了世界领先行列.