Notions of an (H,X)-bialgebroid and of its dynamical representation are proposed. The dynamical representations of each (H,X)-bialgebroid form a tensor category. Every dynamical Yang–Baxter map R(λ) satisfying suitable conditions, a generalization of the set-theoretical solution to the quantum Yang–Baxter equation, gives birth to an (H,X)-bialgebroid AR. The categories of L-operators for R(λ) and of dynamical representations of AR are isomorphic as tensor categories.

This paper shows what is really happening in Picard-Vessiot theory. Our Hopf algebraic approach simplifies and generalizes the theory. Among other things the generalization gives a Picard-Vessiot theory for positive characteristic, for fields with not necessarily commuting derivations, and even for fields with (a set of) higher derivations.

The effect of chemical etching by HF solution on the photoelectrochemical performance and photocatalytic activity of visible light-responsive TiO2 (Vis-TiO2) thin films prepared by a radio-frequency magnetron sputtering method has been investigated. It was found that Vis-TiO2 thin films treated with HF solution (HF-Vis-TiO2) exhibit a remarkable enhancement of the photoelectrochemical performance not only under UV but also visible light irradiation as compared to untreated Vis-TiO2. The incident photon to current conversion efficiencies reached 66 and 9.4% under UV (λ = 360 nm) and visible light (λ = 420 nm), respectively. The HF-Vis-TiO2 thin films have a larger surface area and higher donor density than Vis-TiO2, indicating that the remarkable increase in the photocurrent may be due to the short diffusion length of the photoformed holes in reaching the solid–liquid interface as well as to the high conductivity. Moreover, the HF-Vis-TiO2 thin films were found to act as efficient photocatalysts for the decomposition of water with the separate evolution of H2 and O2 from H2O under visible or sunlight irradiation.

as follows: $\Gamma$ takes $M\in R\mathcal{M}$ to $P\otimes_{R}M\in s\mathcal{M}$ and $\Delta$ takes $N\in s^{\mathcal{M}}$ to $Q\otimes_{S}N\in R\mathcal{M}$ . The isomorphisms $\gamma,$ $\delta$ come from $\alpha,$ $\beta$ respectively. When $\mathcal{A},$ $\mathcal{B}$ are monoidal categories, the 4-tuple $(\Gamma, \Delta, \gamma, \delta)$ is called a monoidal equivalence data if in addition $\Gamma,$ $\Delta$ are monoidal functors and $\gamma,$ $\delta$ are isomorphisms of monoidal functors. A basic example of a monoidal category is provided by $R\mathcal{M}_{R}$ the category of all R-bimodules. For R-bimodules $M,$ $N$, the tensor product $M\otimes_{R}N$ (of $M_{R}$ with $RN$) has an R-bimodule structure (coming from $RM$ and $N_{R}$). Together with unit $R$ , this tensor product makes $R\mathcal{M}_{R}$ into a monoidal category. A natural question arises: What happens if we consider monoidal equivalence data between bimodule monoidal categories $R\mathcal{M}_{R}$ and $s\mathcal{M}_{S}$ ? We begin with two simple examples of monoidal equivalence data. Let

Let H be a Hopf algebra, and A,B be H-Galois extensions. We investigate the category MBHA of relative Hopf bimodules, and the Morita equivalences between A and B induced by them.

A 16 Mb embedded DRAM macro in a fully CMOS logic compatible 90 nm process with a low noise core architecture and a high-accuracy post-fabrication tuning scheme has been developed. Based on the proposed techniques, 61% improvement of the sensing accuracy is realized. Even with the smallest 5 fF/cell capacitance, a 322 MHz random-cycle access while 32 ms data retention time which contributes to save the data retention power down to 60 mu W are achieved.

The modularity of a ribbon Hopf algebra is characterized by the Drinfeld map. An elementary approach to Etingof and Gelaki's (1998, Math. Res. Lett.5, 119–-197) result on the dimensions of irreducible modules is given by deducing the necessary identities involving the matrix (Sij) from the well-known orthogonal relations of Hopf algebra characters.

By means of braiding systems, it ib shown that for a Yang-Baxter coalgebra (C.sigma) there is a coalgebra map of C Into a Hopf algebra H such that sigma extends to a coquasitnangular structure on H if and only if sigma is skew-invertible.

This paper presents a 0.18-/spl mu/m merged DRAM/Logic technology having a 0.45-/spl mu/m/sup 2/ stacked capacitor cell. A low-temperature Metal/Insulator/Silicon (MIS) capacitor process provides high storage capacitance in the small cell, as well as a fully compatible process with high-performance CMOS logic technologies. A robust Co-salicide technology eliminates additional process steps for a silicide block. A developed 4 Mbit test vehicle achieves a retention time of 16 ms at 110/spl deg/C even with a CoSi/sub 2/ layer remaining on all diffusion regions in the memory cells.

Hopf algebras in braided tensor categories are studied with emphasis on finite (i.e., rigid) Hopf algebras. By imitating Larson and Sweedler's (1969) Hopf module construction, it is proved that the antipode of a finite Hopf algebra is an isomorphism of the category and that the left or right integral space is an invertible object. Diagrammatic methods are effectively used throughout the arguments.

The notion of the cylinder product on a coquasitriangular bialgebra and a cylinder matrix for a Yang–Baxter operator is introduced and illustrated explicitly in the case of Oq(M(n))

In a recent human body model (HBM) test for non-wired pins of large-scale integrated circuits (LSIs), the LSIs have failed at lower voltage in comparison with the test for wired pins. The failure voltage agreed with the sparking voltage between the non-wired and the adjacent pins. A transient response simulation with a sparking gap showed that the low failure voltage was caused by the low parasitic capacitance on the nodes of non-wired pins. Although these data indicate the electrostatic discharge (ESD) sensitivity of LSIs, the conventional HBM tester could not control the low capacitance. We conclude that the charged device model (CDM) test with variable capacitance or the machine model (MM) test with low capacitance should be carried out besides the HBM test. Application of these data gives us a method to protect quarter-micron LSIs from ESD troubles.

The conventional charged device model (CDM) test methods for large-scale integrated (LSI) circuits have not prescribed the device capacitance; furthermore, the CDM sensitivity has been represented by the withstand voltage. Also, a method for measuring the voltage of small objects such as LSI circuits has not been established. For these reasons, the failure voltages obtained with every kind of tester have varied, and it could not be judged whether the charged LSI circuit would fail or not in CDM events. To solve these problems, we defined the failure factor as the excess mobile charge which could be measured by the newly developed coulomb meter. In addition, we developed a new CDM tester with the coulomb meter and obtained the excess mobile charge and the device capacitance. The CDM tester showed that several logic MOS LSI circuits failed at their inherent constant charge. However, when the charge in low capacities was measured by the coulomb meter, the internal circuit showed a step transient response. This problem could be alleviated considerably by replacing the metal probe with a ceramic one. By using this coulomb meter, we investigated the basic characteristics of the device capacitance. Consequently, the device capacitance versus the distance between the LSI circuit and the ground plane and the relationship between each pin's capacitance and the applied voltage became clear. In conclusion, the basic failure factors in the CDM could be made clear; then it could be judged by the coulomb meter whether the charged LSI circuits would fail or not in CDM events.

In the charged device model (CDM) test, the relationship between the failure voltage, the capacitance of LSIs and the failure charge was made clear by a new CDM tester. The mobile charge measurement apparatus was fabricated in the tester, and the capacity and the charge could be measured simultaneously in the CDM test. The CDM sensitivity of the logic MOS LSIs was represented as an inherent quantity of charge for each LSI. Furthermore, using the experimental results, a basic protection circuit to withstand the high quantity of charge in the CDM test was described. The practical use of the data gives us methods to prevent electrostatic discharge (ESD) trouble for quarter-micron LSIs.