Unified Shader Array is the computation core of the Unified Shader Array GPU, and the shader cores are the basic shader unit. In order to support the large-scale and thread-level parallelism of GPU, a large number of streaming processors composed of shader cores are set in GPU. The streaming processors can enable GPU to implement thread-level parallelism in the way of SIMD or SIMT. At the same time, GPU deploys large-scale register files for the streaming processor to reduce the cost of context switching, so the management of register files is of great significance to GPU performance. In the traditional GPU, each shader core has a unique register file, which simplifies the hardware management of the register. However, it will cause the limitation of the shader core’s scale and insufficient register utilization. Based on the domestic special GPU, this paper analyzes the traditional GPU register scheduling strategy and carries out the design of the unified shader array shared register file based on pure hardware to reduce the cost of shader cores. This paper introduces its implementation in detail, including dynamic allocation and collection management of register files, allocation of multiple registers for thread bundles, detecting and handling of bank conflicts, and related register allocation and release collection instructions. Finally, we complete the RTL code implementation and analyze the experimental results. The results show that the design of this paper has reached the expected design goals in terms of simulation and logic synthesis.

With the rapid popularization and rapid development of embedded devices such as mobile terminals, people have become increasingly demanding for high-resolution picture rendering effects and fast computing capabilities of various processors. The enhancement of these capabilities of the processor depends on the computer’s floating-point computing capabilities, which makes people to the GPU’s rendering quality and speed, mobile devices, digital signal processing (DSP), and other computing units’ floating-point computing capabilities Higher requirements have been raised [1]. The transcendental function arithmetic unit based on single-precision floating-point numbers is a very important component in these devices. For example, the perspective division, vector normalization, and coordinate transformation required in the GPU all require transcendental function operations [2] (For example, find the inverse, square root, trigonometric function, exponent, logarithm, etc.). In addition to the algebraic operations implemented in the field of mathematics, it is difficult to directly use a computer to calculate some complex functions. It can only complete complex functions through a limited number of simple operations, but for transcendental functions, in other words, the relationship between their input variables and output variables cannot be expressed by a finite number of basic operations such as addition, subtraction, multiplication, division, and power. Therefore, in a computer, the operation of a transcendental function cannot be directly implemented using a limited number of basic function operation units. A special operation unit is required to complete the operation of the transcendental function.

Unified Shader Array (USA) is the computing core of the Unified Shader Array Graphic Processing Unit (GPU), and the shader cores is the basic shader Unit of the Unified Shader Array. In order to support the large-scale thread-level parallelism of GPU, a large number of streaming processors composed of shader cores are set in GPU. The streaming processors (SP) can enable GPU to implement thread-level parallelism in the way of Single Instruction Multiple Data (SIMD) or Single Instruction Multiple Threads (SIMT). At the same time, in order to reduce the cost caused by context switching, GPU deployments a large scale of register file resources at the bottom level for the use of the streaming processor. So the management and use of register file is of great significance to the performance of GPU. The unique register file for each shader cores in the traditional GPU simplifies the register management hardware, but at the cost of insufficient register utilization. It will cause the disadvantage of limited size of shader cores. This paper introduces the current research status of various technologies at home and abroad from the aspects of register file sharing, high resource utilization and low power consumption.

随着处理器设计技术和半导体制造工艺的进步,芯片的规模和复杂度急剧增大,不断提升的功耗密度对系统工作的可靠性和稳定性造成很大影响,"功耗墙"已经成为提升处理器性能的最大障碍.介绍了低功耗设计的基本原理,结合X86指令集的特点,设计了一种X86指令译码器,并在体系结构层次上,提出从指令预取队列和译码队列两个不同角度对X86指令译码器进行低功耗设计的方法.基于SMIC 180 nm CMOS工艺,采用Synopsys DC工具进行了综合实现,并对译码器低功耗设计效果进行了评估.结果表明,在几乎不影响速度和面积的前提下,指令译码器关键数据通路寄存器平均翻转率降低了17.16％.

为解决传统Catmull-Rom缩放结构因行列计算量比例不协调导致行/列插值部件长期停顿而造成的性能低下问题,提出了两种自适应结构.在传统结构的基础上增加三个插值部件,并结合两种自适应策略,分配新增插值部件用于行或列插值,并对处于工作状态的插值部件的数量进行调整,得到两种自适应结构.实验表明:与传统结构相比,结构一各类资源占用为原来的1～2.5倍,而性能提高最大为原来的3.99倍,但仅在缩小时存在性能提升,适用于仅存在缩小的场合(如纹理的MIPMAP);结构二各类资源占用为原来的1.7～2.5倍,而性能提高最大为原来的3.98倍,在缩小与放大时均存在性能提升,适用于放大缩小同时存在的场合(如图像的缩放).

为实现图形处理器的自主可控, 设计了面向 OpenGL 2.0 图形处理器图像处理单元的体系结构. 首先, 确定了图像处理单元的单元结构及工作流程; 其次, 针对每条所处理的函数设计了数据通路; 随后, 依据各函数的数据通路和OpenGL规范, 整理了各模块的处理函数对照表; 最后, 实现了其体系结构, 并在虚拟仿真和FPGA平台进行了纹理加载/获取、卷积、颜色表、柱状图等功能验证, 对纹理加载进行了峰值性能验证, 面向 FPGA 和 ASIC 进行了代价评估. 结果表明, 该结构能够实现图像处理单元所规定的系列功能, 性能满足设计要求, 峰值情况每秒可处理30帧2K×2K图像, 实现代价可接受. 目前, 该图像处理单元已集成到完全自主研发的图形处理器之中.

数字图像处理技术的高速发展需要更加强大的高性能图形处理器提供支持.为了满足图形处理器在RGB颜色空间进行视频图像处理时,可以单独改变某个颜色属性(色度、饱和度或亮度)来调整视频图像显示效果而不影响其它属性的需求,本文研究一种流水处理的HSV调整电路的设计与实现.采用RGB到HSV颜色空间转换、HSV调整和HSV到RGB颜色空间转换关键模块设计电路,重点实现了核心模块HSV调整.最终,通过模块级仿真验证、系统级虚拟仿真验证和FPGA原型验证完成了HSV调整电路的验证实现,验证结果表明本设计功能和性能满足需求,实现了流水处理的HSV调整功能,从而达到理想的视频图像处理效果.

One of the most important design aspects for high-end GPU is improving its power efficiency.Data compression can be used in various stages of the GPU 3D rendering pipeline to reduce off-chip memory traffic,yield high performance and low power consumption.In order to summarize the research progress and application status of data compression techniques for GPU pipeline,this paper outlined the key features of data compression specialized for buffer objects and texture based on the structure characteristics of GPU 3D rendering pipeline and memory system.Moreover,it discussed research status,inefficiencies and challenges of data compression in GPU pipeline.In the end,it indicated the further research content for GPU data compression according to application demands.

提出一种面向GPU统一染色阵列的并行自适应看门狗——PWDG,为GPU统一染色阵列中每个基本的并行计算单元关联一个看门狗,多个看门狗可以根据任务负载变化情况,实现对GPU统一染色阵列计算资源的并行自适应监控,具有可配置、低功耗、错误定位精确的特点,降低了设计和调试难度,方便应用.基于统一染色架构GPU设计并实现了PWDG,并基于虚拟仿真平台和Xilinx FPGA构成的原型系统对PWDG进行了验证,结果表明PWDG各项功能正确,能够满足GPU统一染色阵列并行自适应监控的需求.

Texturing is an indispensable functionality of GPU. To against the texture look-up operating speed and texture memory bandwidth problem, this paper presents a dedicated hardware architecture of texture engine for 3D graphics engine based on OpenGL 3.0 and GLSL 1.40 with a number of novel features, such as an optimized full-purpose four-way pipelined Parallel texel data formatters and filters, multi-port multi-bank non-blocking texture cache. The design of the texture engine is synthesized under SMIC 40 nm CMOS process technology. Performance evaluation results show that the design can achieve up to 33 fps for 1024×768 resolution at 150 MHz and is efficient for real time rendering.

Researches on critical issues of video graphics array (VGA)adapter and techniques of VGA mode for graphic process unit were carried out for needs of GPU VGA mode of aviation applications.The related works of GPU and VGA mode were re-ported.The related foundation for VGA mode design was presented.The key issues of VGA adapter were analyzed including VGA work mode,components of early VGA adapter,VGA registers and video BIOS.Techniques could be used in VGA mode design of GPU were proposed,involving the design techniques of VGA hardware and video BIOS.The research indicates that the support of super VGA was the next work of GPU VGA mode.

To improve executing efficiency of 2D graphics operations ,a parallel processing accelerator for typical 2D graphics , image and text was proposed .Functional verification and performance evaluation were carried out on FPGA prototype system constructed using Xilinx Virtex6 xc6v1x760 .As a result ,compared to Marvell PXA300 ,the accelerating engine has an obvious improvement on accelerating 2D graphics operations .Compared to software rendering ,when 2D graphics operations are executed on the accelerating engine ,it can be speeded up by 23 times on average .Its operating frequency can reach 325 MHz using SMIC 65nm CMOS technology ,which meets design requirements .

设计自主知识产权的图形处理器(Graphic Processing Unit,GPU),对国家信息安全和机载图形芯片的自主保障意义重大.为满足机载应用的双路显示需求,设计并实现了支持双路显示的GPU显示控制单元.通过加入视频输入模块,使其具备视频输入功能;通过设置两条显示处理通路,使其具备双路显示功能,支持两路视频的独立、复制和拼接显示;通过在显示处理通路中加入叠加及HSV、Gamma和RGB调整模块,使其具备视频、图形及光标的叠加及多种色彩调整功能;通过集成多种类型接口,使其支持多种显示设备.构建了仿真验证平台和FPGA验证平台对显示控制单元进行验证,其结果表明,设计功能正确、性能满足要求,可用于GPU芯片设计.目前,该单元已集成到某GPU IP之中,并已完成FPGA验证.

Based on network calculus,a technique was proposed for analyzing communication delay bounds for individual flows in Networks on Chip(NoC)using Improved Asymmetric Multi-channel Structure(IAMCS)of router.The flow control blocking,switch blocking and channel blocking of IAMCS router were analyzed. Then,corresponding equivalent service models of them were constructed.By extending the router service model to the analysis of the entire network,the forward equivalent service analysis network was established.Furthermore,using the contention tree model, the equivalent service curves were computed for individual flows in the equivalent service analysis network,and then their delay bounds were derived.Experimental results show that the delay bound model can restrict the maximum delay of simulation,and the bounds is compact.

The entire design space is extremely large,and there is huge difference of performance between different options.So performance evaluation of different design becomes an important issue in initial stages.The paper took mode-ling-based performance evaluation methodology as masterstroke,discussed research status and metrics of evaluation methods which include simulation modeling and analysis modeling,and summarized accuracy estimating methods of NoC evaluation models.Also,a comparison was made between methods mentioned above.Finally,a guidance of future research was proposed based on the analysis of future challenges.

To solve low-power mapping with bandwidth and latency constraints of network-on-chip (NoC), a fusion mapping with genetic and ant algorithms is proposed. Several optimal solutions are obtained by quick searching of genetic algorithm, then the initial values of ant paths are assigned according to the order of these optimal solutions to initialize the pheromone distribution of ant algorithm. Resorting the ant algorithm with crossover and mutation operation, and taking full advantage of the positive feedback features of the ant algorithm, the exact solution of the low-power mapping is searched out. This fusion strategy can be used to solve the large-scale NoC mappings with good optimization precision and convergence. The experimental results indicate that this strategy obviously outperforms genetic and ant algorithms for larger scale systems, the improvement of search rate can be heightened up to 220.3% for system of 64 processing elements, and the optimization difference gets less than 9.1% compared with ant algorithm.

To improve the performance of the router,an improved asymmetric multi-channel structure(IAMCS) was proposed.Besides,the corresponding queueing theory analysis model was presented for performance evaluation of network on chip(NoC) design.By extending the number of channels of asymmetric multi-channel structure′s input port from single to a group,the head-of-line blocking for specific direction was reduced.Then,through analyzing various blockings,packet arrival rate,service rate,and resorting to M/G/1/N queuing theory system,the analysis model was constructed.With proper number of channels in the group,IAMCS can efficiently reduce the average packet latency and increase the saturation throughput.Moreover,the mean relative error between the presented analysis model and simulation results is less than 6.4%.

To solve the power optimization of network-on-cship(NoC) with voltage-frequency islands(VFIs),power-aware NoC mapping with performance constraints was formulated.An optimization method based on fusion of genetic algorithm and ant algorithm was proposed.With considering the power consumption of processors and level shifters between different VFIs besides the communication during the mapping,the algorithm makes much progress in optimization and reduces the overall power consumption of system.Through fusing genetic algorithm and ant algorithm together,and taking advantage of the fast searching ability of genetic algorithm and precise optimization capabilities of ant algorithm,the optimized algorithm takes convergence speed into account as well as optimization precision.Experimental results show that the proposed algorithm can significantly reduce the power consumption of NoC with VFIs and meet its performance requirements simultaneously.Experimental results also indicate that the algorithm has good optimization precision,fast convergence,and is suitable for solving the large-scale NoC mapping problems.

Multi-operand adder is one of attractive solutions compared with a network of 2-operand adders for accelerating algorithms including a lot of addition operations. In this paper, an improved 3-operand floating-point (FP) adder has been presented. Firstly, the internal width of the adder has been given which is compatible with IEEE-Std754. Secondly, a realignment method processing sticky bits is used to make the architecture has the same accuracy with a FP adder which has a infinite internal width. Thirdly, a low cost method to detect catastrophic cancellation has been employed. Several sophisticated techniques, such as compound adder and Leading zero anticipation (LZA), are utilized to optimize the architecture. The implementation results show that the proposed architecture has a competitive area and delay by comparing with both a basic 3-operand FP adder and a network of 2-operand FP adders. A small data format version of the proposed architecture has been verified by an exhaustive testing.

The Improved Asymmetric Multi-Channel Structure can effectively reduce the head of line blocking and provide an efficient promotion for the router performance. However, allocating channels in channel groups (CGs) uniformly will cause the buffer wasting and the power significant increasing. To resolve this issue, we present a novel channel planning algorithm which can customize the router design in Network-on-Chip (NoC). More precisely, given the traffic characteristics of the target application and the channel budget, our algorithm automatically assigns the channel number for each CG, in different input ports across each router, to match the traffic pattern, such that the overall power consumption is minimized. Experimental results show that, compared with channel uniform allocation, about 15~27% savings in power consumed by buffer can be achieved by our algorithm, while having the similar performance meanwhile.