The segmented power supply scheme for long-stator linear motor facilitates reducing power capacity and achieving a high power factor. However, the segment-switching process leads to overcurrent under high-speed conditions. This paper proposes a novel segment-switching strategy based on the time-optimal control theory. It employs time-optimal feedforward voltage and planned current trajectory during the switching transient process. Thus, it ensures rapid disconnection of the exiting segment and rapid establishment of the current in the incoming segment, while suppressing transient current overshoot. The mathematical model of the long-stator linear motor is established in the process of segment-switching. It derives the minimum times required to force the exiting segment current to zero and to establish the incoming segment current to the reference value by time-optimal control theory. Furthermore, the time-optimal voltages and current trajectories are calculated. The time-optimal current trajectories are used as the reference command for the current loop. The time-optimal feedforward voltages are introduced into the current loop control. Hence, it achieves rapid disconnection of the exiting segment and fast, accurate establishment of the incoming segment current. Experimental and simulation results collectively validate the effectiveness of the proposed segment-switching strategy.

With the advantages of low control complexity and high efficiency, series resonant dc-dc converters (SRCs) have been widely used in application scenarios that require galvanic isolation. To improve power density, it is desirable to use as small dc capacitors as possible. However, the operating characteristics under both normal and faults conditions of SRCs exhibit substantial discrepancies if the dc capacitors decrease significantly. To address this issue, the characteristics of the SRC operated with small dc capacitors is analyzed under semiconductor devices open circuit and short circuit faults conditions. On this basis, a fault tolerant strategy is proposed, with which soft switching can still be achieved in case of semiconductor devices faults. Both of the efficiency and the reliability of the SRC have been enhanced. The correctness of the theoretical analysis and the performance of the proposed fault tolerant strategy are validated through experimental results.

The second harmonic current (SHC) is significant in the cascaded H-bridge converter with dc-dc stage and supercapacitor under high current and variable output frequency, increasing the risk of overcurrent in the dc-dc. Conventional suppression strategies designed for fixed-frequency SHC constrain the dc-dc controller bandwidth to the SHC frequency, inevitably degrading dynamic performance. To address this issue, this article proposes a feedforward-based SHC suppression strategy. By analyzing the transmission path of SHC, an accurate feed-forward compensation is introduced at the dc voltage reference point, blocking the second harmonic signal from entering the dc-dc control loop. This decouples the SHC suppression strategy from the controller, eliminating the bandwidth constraint imposed by the SHC frequency. Therefore, the proposed strategy ensures both effective SHC suppression and enhanced dynamic performance under variable frequency conditions. Furthermore, the dc-dc controller design process is significantly simplified. Finally, the experimental results validate the effectiveness of the proposed SHC suppression strategy.

Existing loss minimization control (LMC) methods for linear induction machine still suffer from poor parameter robustness and limited effect on system loss suppression. To solve these issues, this article proposes a robust LMC method for three-level inverter-fed LIM drive system under low switching frequency of linear metro. First, a hybrid optimal primary flux search method is proposed to select the optimal flux reference, where the loss model and the gradient descent method are combined for system loss minimization and robustness enhancement. Second, an ultralocal model-based predictive flux control with two-step prediction optimization is developed to flexibly manipulate optimal flux under low switching frequency. By observing the lumped disturbance, the reference voltage vector (VV) independent of parameters can be obtained for optimal VV determination. Moreover, after incorporating with the magnetizing inductance identification-based flux observer, the parameter robustness of the core parts in existing LMC methods, i.e., flux observation, optimal flux selection and manipulation, has been significantly enhanced. Finally, comprehensive simulation and experiment have been conducted, showing that compared to the existing LMC method, the system loss is further reduced by 1.9% and 5.3% under accurate parameters and mismatched parameters, respectively.

Combining Si-IGBT and SiC-MOSFET in a hybrid parallel configuration integrates the lower conduction loss characteristics of Si-IGBT with the fast switching and lower losses of SiC-MOSFET. This hybrid approach offers significant advantages in improving the efficiency of power switching devices. However, the effects of different drive delays on switching losses between Si-IGBT and SiC-MOSFET are not well understood. Improper designing results in higher switching losses instead of lower switching losses, which can seriously affect the safety and reliability of the switching device. This work establishes a switching loss analysis model that takes into account the effects of drive delay. Simulation analysis of the switching losses in a hybrid parallel double-pulse circuit with different gate drive time delays for turn-on and turn-off was conducted to determine the optimal delay time for minimizing the switching losses. The simulation results show that under the proposed optimal delay timing, the turn-on losses are reduced by 32

The hybrid modulation strategy (HMS) offers the advantages of simple voltage balancing and low current harmonic distortion, rendering it suitable for the cascaded H-bridge (CHB) inverter with supercapacitor (SC) and dc–dc stage. The rounding function is essential in the HMS-based voltage balancing method, as it determines the number of the inserted submodules (SMs) within each control cycle. However, the voltage fluctuations in the dc-link among the SMs may either increases or decreases, affected by the rounding function employed. To explore this, three common rounding functions are considered, including fix(x), round(x), and ceil(x). Among these dc-link voltage fluctuations under the three functions, fix(x) yields the lowest, followed by round(x), and ceil(x) results in the highest fluctuation. Simulation and experimental results demonstrates the correctness of the theoretical analysis in this paper.

This paper explores the challenges and design considerations of multilevel energy storage converters (MESC) tailored for high-power applications, with a particular focus on high-power linear motor drives. The research evaluates different converter topologies including cascaded H-bridge (CHB) and modular multilevel converter (MMC) to identify configurations that optimize power delivery, energy management, and operational efficiency. The selection and analysis of these topologies are driven by the need to address increasing demands for energy efficiency and system reliability in high-power settings. The paper aims to guide the design choices by highlighting the critical factors that influence converter performance and system integration.

Low switching frequency of power semiconductor devices is expected to decrease losses in the cascaded H-bridge (CHB) inverter with supercapacitor and dc–dc stage. This paper proposes a switching frequency reduction method accompanied by a hybrid modulation strategy (HMS) for the CHB inverter. By optimizing the comparison output between the reference wave and the triangular carrier, unnecessary state jumps in the switching signals for the H-bridge can be avoided when rotating the switching mode of the H-bridge in the HMS. The proposed method can reduce the average switching frequency among the H-bridges without side effects on capacitor voltage balance and ac outputs. Finally, its effectiveness is demonstrated through simulation results of five SMs based on MATLAB/Simulink.

Linear motors with stator segmented powered are widely used in high-speed electromagnetic propulsion applications. And fast and smooth segment switching is required to achive higer propulsion speed. In this paper, the dynamic characteristics of the current during the segment switching process are analyzed. And the upper and lower limits of the electrical angle required to complete the segment switching at any speed are obtained by calculation. Then, a novel segment switching method is proposed, which achieves fast switching without overcurrent at any speed. Simulation results verify the effectiveness of the proposed segment switching method.

To reduce capacity of converters, segmented power supply method is usually adopted for linear motors (LMs), and thyristor-based switches, which is composed of anti-parallel thyristors, are used to achieve power supply switching. However, thyristor-based switches can only be turned off at the moment of current zero crossing point, which may lead to overcurrent of LMs during power supply switching process. The operating characteristics of the LM is analyzed for the duration of the power supply switching, and the switching time is also derived. On this basis, a smooth power supply switching method is proposed in this paper. The proposed method can achieve thyristor-based switches of all phases turning off simultaneously, while also avoiding overcurrent. The effectiveness of the proposed method is verified by simulation results.

Segmented power supply of Linear motors (LMs) is usually adopted for the purpose of reducing converter capacity and improving efficiency. In high-speed occasions, thyristor-based switches are always employed to achieve power supply switching for segmented LMs. However, thyristor-based switches can only be turned off at the moment of current zero crossing point, leading to unbalanced operations and overcurrents of LMs during power supply switching duration. To address this issue, the current dynamic characteristics of the LM is analyzed, and the analytical expressions are also derived during the turning off process. Furthermore, an improved power supply switching method is proposed to complete fast switching and to avoid overcurrent. Finally, the correctness of the presented analysis and the effectiveness of the proposed method are both validated by simulation results.

To improve power transmission efficiency and power density, a novel medium voltage inverter topology is proposed. It consists of a current source actively commutated converter (ACC) and a three-phase voltage source converter (VSC). It is operated in a fundamental frequency switching mode for ACC. The switching frequency of the internal power semiconductor device is consistent with the grid frequency which reduces switching losses of devices, significantly. The proposed three-phase VSC is capable of suppressing the current harmonics and compensating reactive components generated by ACC while undertaking partial power transmission, ensuring high power quality on the grid side. It integrates a small amount of energy storage capacitors internally for the proposed medium voltage inverter which effectively reduces system weight and volume. Moreover, the matched control strategy is also proposed. Simulations on a 1MVA 10kV ac/ 15kV dc medium voltage inverter by Matlab/Simulink verify the effectiveness of the proposed topology and control strategy.

For the cascaded H-bridge (CHB) inverter, significant disparity in active power distribution among the submodules (SMs) may destabilize it. This paper presents an improved capacitor voltage balancing method for scenarios where some SMs are involved in zero active power input. A hybrid modulation strategy (HMS) is employed for the H-bridges to balance the dc-link capacitor voltages through voltage sorting. Furthermore, to prevent over-modulation of any H-bridge, the H-bridge reference voltages for these SMs with zero active power input are reconfigured. Importantly, the number of proportional-integral (PI)-based inner-phase voltage balancing controllers can be reduced to one. Finally, simulation results using MATLAB/Simulink for four SMs demonstrate the effectiveness of the presented method.

In the cascaded H-bridge inverter (CHBI) with supercapacitor and dc-dc stage, inherent second-order harmonic power flows through each submodule (SM), causing fluctuations in both the dc-link voltage and the dc-dc current. There exist limitations in handling these fluctuations at variable output frequencies when employing proportional-integral (PI) control to the dc-dc stage. This paper aims to coordinately control these second-order harmonic voltage and current fluctuations in the CHBI. The presented method configures a specific second-order harmonic voltage reference, equipped with a maximum voltage fluctuation constraint and a suitable phase, for the dc-dc stage. A PI-resonant controller is used to track the configured reference. This allows for regulating the second-order harmonic fluctuation in the average dc-link voltage among the SMs within a certain value. Importantly, the second-order harmonic fluctuation in the dc-dc current can also be reduced. Simulation and experimental results demonstrate the effectiveness of the presented method.

This article presents a coordinated balancing charging strategy for the cascaded H-bridge inverter (CHBI) with supercapacitor (SC) and dc–dc stage by adopting multistage adjustment of the SCs’ charging powers. The power distribution constraints among the submodules (SMs) are analyzed to prevent over-modulation of the H-bridges. The reactive power distribution is optimized to expand the stable operation range of the CHBI in case of significant disparity in the active power distribution among the SMs. The relationship among the charging powers of different SCs is also derived under the aforementioned constraints. Finally, the effectiveness of the presented strategy is verified through the experimental results on a 16-kW CHBI single-phase prototype with four SMs.

Cascaded H-bridge inverter (CHBI) with supercapacitors (SCs) and dc-dc stage shows significant promise for medium to high voltage energy storage applications. This paper investigates the voltage balance of capacitors within the CHBI, including both the dc-link capacitors and SCs. Balance control over the dc-link capacitor voltages is realized by the dc-dc stage in each submodule (SM), while a hybrid modulation strategy (HMS) is implemented in the H-bridge to balance the SC voltages among the SMs. Meanwhile, the dc-link voltage fluctuations are analyzed under the HMS. A virtual voltage variable is introduced to coordinate the balancing of dc-link capacitor voltages and SC voltages. Compared to the balancing method that solely considers the SC voltages, the presented method reduces the dc-link voltage fluctuations without affecting the voltage balance of SCS. Finally, both simulation and experimental results verify the effectiveness of the presented method.

The Cascaded H-bridge energy storage converter provides power to ultra-high-speed linear motors. During motor acceleration and braking, rapid frequency-changing second harmonic currents are generated in the submodule inductance branches. To address this issue, this paper proposes an improved mathematical model for its submodules and utilizes a disturbance observer established based on this model to rapidly track this harmonic current. By employing control with disturbance current feedforward, variable-frequency second harmonic currents can be effectively suppressed without compromising the dynamic response speed of the DC-DC converter. Simulation results confirm the effectiveness of the proposed method.

In high-speed applications, thyristor-based switches are usually used to achieve fast power supply switching for segmented linear motors. However, thyristor-based switches can only be turned off at zero-crossing of currents, which makes stator currents seriously asymmetric during switching process, leading overcurrent. In this paper, the current dynamic characteristics of two segments involved in power supply switching are analyzed, and the analytical expressions of the both stators' currents are also derived during switching process. Furthermore, the required electrical angle to complete turn-off and the maximum current at the converter side are obtained through numerical calculation method. Based on the aforementioned analysis, a power supply switching method is proposed, featuring both fast switching and overcurrent suppression. Simulation results verify the correctness of the presented analysis and the effectiveness of the proposed switching method.

A half controlled actively commuted converter (ACC) is proposed in this paper to reduce the number of controlled semiconductor devices. For the proposed half-controlled ACC, it contains only half controlled devices than the fully controlled ACC. Moreover, a lower switching frequency modulation strategy is also proposed with which each device is only turned on and off once during each grid cycle. Although the switching frequency is reduced, a multi-winding phase-shifted transformer can effectively eliminate the low order and even harmonics of the modulated output current. Simulations on a 1000MW/ 500kV ac/ +/- 350kV dc half-controlled ACC validate the effectiveness of the topology and modulation strategy.

The Cascaded H-bridge energy storage converter (CHBESC) integrates energy storage components within cascaded multilevel converters to deliver short-term high power to the stator of ultra-high-speed linear motors. This integration effectively mitigates the impact on the power grid. However, during the acceleration and braking of the ultra-high-speed linear motor, the frequency of the CHBESC output voltage varies with the motor speed. This variation causes the frequency of secondary harmonic currents in the submodules to fluctuate accordingly. To address this issue, this paper establishes an analytical model for secondary harmonic voltage and current over a wide frequency range. The study investigates the fluctuation patterns of these harmonics under different control and circuit parameters, providing theoretical guidance for the design of circuit parameters and controllers. Simulation results validate the accuracy of the model and the effectiveness of the parameter design guidance.