ZUC-256 is a more secure stream cipher based on ZUC-128 developed independently by China, which emerged mainly to cope with the advent of 5G communication and the post-quantum cipher era. Based on the ZUC-256 encryption algorithm, this paper focuses on its working phase and proposes two optimization methods for the working phase, one is a pipelined structure that focuses more on increasing the frequency, and the other is based on the specificity of the modulo operation in the algorithm, which focuses on reducing the resource overhead. The final validation results show that the first method increased frequency by 37.2% and the second method reduced resource overhead by 18.7%. These two optimization methods show that the ZUC algorithm is quite flexible in balancing different throughputs with resource overheads.

通用矩阵向量乘法(GEMV)函数是整个二级基础线性代数子程序(BLAS)函数库的构建基础,BLAS作为关键基础计算软件之一,目前在申威处理器上却没有一个高性能实现的版本.针对上述问题,为充分发挥申威1621平台的高性能BLAS库计算优势,提出一种基于申威1621的通用矩阵向量乘法的性能分析与优化方法.首先对GEMV函数进行计算重排序、循环分块的改进;然后采取单指令多数据流(SIMD)以及指令重排的优化方式;最后对内存分配方式进行择优选择.测试结果表明,GEMV函数平均性能达到GotoBLAS版的2.17倍.在使用堆栈分配内存空间或增加对y向量步长的判断分支两种方案后,相较于GotoBLAS,小规模矩阵的平均性能由2.265倍提升至2.875倍.为提高大规模矩阵的性能,以及发挥申威1621多核处理器并行机制,在开启4线程后,平均性能达到单核的3.57倍.因此,优化后的GEMV函数在申威平台上较好的体现了并行效果.

The national secret SM3 cryptographic hash algorithm is to generate a fixed hash value after iterative compression and expansion of a group of messages, which is mainly suitable for the generation of digital signatures and random verification codes. The algorithm is based on the hash calculation, which is a computationally intensive task with high computational intensity. In order to improve the operating efficiency of the algorithm, make it achieve optimized operating effects on a multi-core system. This article uses multi-threaded parallel to rewrite the algorithm in parallel: through the privatization of variable attributes to avoid memory read and write conflicts in multi-threaded parallel, through dynamic task scheduling to achieve multi-threaded load balancing, so as to realize the parallel version of SM3 algorithm. Experimental results show that the parallel algorithm has a good linear acceleration when the number of threads increases, and the speedup ratio is increased by 2-6 times compared with the serial algorithm, which can provide a reference for the performance improvement of the algorithm on multi-core computing components.

低精度浮点数常用于深度学习加速,目前申威平台缺乏对低精度浮点数的支持,数学库的设计往往需要结合数据类型与处理器特点定制算法才能发挥出最大优势,旨在为申威1621平台设计一套支持半精度计算的超越函数.通过分析各类浮点数特性,结合申威1621的结构特点提出一种基于回乘取余查表算法.首先,对函数的定义域进行归约,生成精简的数据表;然后将回乘取余后的数值按照sign、exponent、mantissa三部分拆分计算索引;最后,查表返回结果.测试结果表明,使用回乘取余查表算法实现的半精度超越函数,相较于基于多项式近似、移位相加等算法的申威数学库及GLIBC开源数学库,性能分别提升了116％和215％.在精度需求不高的应用中既保证了正确性又大幅度提升了数学函数计算效率.

当前的MD5解密算法无法适应申威架构,不能充分发挥申威26010众核处理器的性能优势.针对上述问题,采用散列初始化、循环展开、链接变量优化、61步优化和申请内存优化等优化方法在单核上进行优化,提高解密算法速度,并且将优化后的解密算法改写成主从模式,将计算任务分配到64个从核中并行执行,对主从核的访存方式进行优化,以减少访存对程序带来的时间开销.通过5组不同任务量的测试,实验结果显示在单核上优化后的平均加速比为12.28,在从核上优化后的平均加速比为44.84.实验结果表明在申威26010众核处理器上的MD5解密算法优化方法具有可行性和有效性.

随着口令恢复的计算需求不断增加,传统的口令恢复工具不能满足实际的计算需求.基于神威OpenACC二次代码开发的优化策略,提出了较好的解决方案.采用申威众核处理器,对Office口令恢复程序进行移植和优化,充分利用众核处理器的从核计算性能和局部存储优势,在加速循环并行化、优化全局访存操作、提高数据传输效率三个方面进行了改进与优化,并通过实验对该方法的正确性、有效性进行了分析和验证.用Office DOC 2007的加密文档作为测试案例,经过多种数据规模测试,并与传统的口令恢复工具和开源的Hashcat口令恢复工具进行了实验对比.实验结果与性能分析表明,该方法能够较好地发挥申威众核处理器的优势,在申威众核处理器上实现Office口令恢复,具有良好的加速比,能有效满足实际的应用需求.

BLAS库作为高性能计算中最基本的数学库,对高性能计算机平台上的数值计算、人工智能等领域应用都起着重要作用.BLAS3级函数GEMM是整个BLAS库性能的核心指标.目前,还没有能够充分发挥申威1621平台优势的高性能BLAS库.针对上述问题,在申威1621平台上,实现了GotoBLAS的移植与优化.提出了一种使用SIMD向量化进行核心代码优化的算法实现,为满足向量优化的算法实现分别进行了数据重排、计算数据块选择、浮点寄存器分配、向量化指令改写等优化技术.分别比较了SGEMM和DGEMM在Micro-kernel中使用cache行和使用向量化优化的最优数据块选择方案.实验结果表明,优化后最佳分块下的SGEMM单核性能比GotoBLAS单核单精度浮点数平均加速52.09倍,DGEMM单核性能比Goto-BLAS单核双精度浮点数平均加速32.75倍.

由于X265编码库目前还不适应申威平台的软件生态环境,造成移植到申威处理器上的X265视频编码库性能较低.为了解决这个问题,通过分析X265编码库中视频编码的各个编码模块,提出了基于申威平台的帧间预测模块优化方法,该方法采用4个线程对帧间预测模块进行优化,提升了X265编码库执行效率,同时解决了多线程中存在的线程数据竞争、分配不均衡和迁移耗时的问题,进一步提升了X265编码库的性能.通过对比6个测试序列优化前后的编码转换时间和PSNR,证明了本文方法的有效性与可行性.

Vectorization of programs is crucial for achieving high performance on modern processors with SIMD (Single Instruction Multiple Data) extensions. Programs with IF-statements suffer from control flow divergence that seriously complicates automatic vectorization. Therefore, contemporary compilers employ the IF-conversion approach to convert control flow to data flow, which relies on using predicated execution techniques (i.e., masked or select SIMD instructions). In this paper, we enhance the compiler's capabilities to generate efficiently vectorized code for processors without masked instructions. We improve the state of the art in program vectorization by developing a novel approach-IF-select transformation-which is applicable to arbitrarily nested IF-statements. We implement our approach in the open-source Open64 compiler and evaluate its performance on the SW26010 processor used in the Sunway TaihuLight supercomputer (currently #3 in the TOP500 list) that does not support masked instructions. We extend our vectorization approach by providing an additional LLVM optimization pass to reduce the amount of masked memory accesses on processors without masked instructions, e.g., IBM Power8 and ARMCortex-A8. Experimental results demonstrate the performance advantages of the suggested vectorization techniques.

伴随着并行体系结构和处理器芯片的发展,计算机系统提供的计算资源越来越多,结构越加复杂,程序员手工编写并行程序的难度也越来越大,自动并行化技术的研究显得愈发重要.首先通过现代体系结构支持的4种并行方式对循环自动并行化技术进行梳理,然后对自动并行化流程进行描述,提出4种循环并行方式并分别进行分析,最后对当前主流产品级编译器的自动并行化能力进行测试和分析,直观反映当前主流编译器的自动并行化能力.

异构众核处理器是面向高性能计算领域处理器发展的重要趋势,但其更为复杂的体系结构使得编程难的问题更加突出.针对这一问题,基于开源编译器Open64,提出了一种面向异构众核处理器的并行编译框架,将程序自动转换为异构并行程序.该框架主要包括4个模块:任务划分模块用来识别适合进行加速计算的程序段,实现了嵌套循环的多维并行识别方法;数据布局模块完成数据在主存和SPM之间的布局,实现了数组边界分析和指针范围分析;传输优化模块实现了数据传输合并、传输外提、打包传输、数组转置等多种数据传输优化方法;收益评估模块在构建代价模型的基础上实现了一种动静结合的收益评估方法.并且,基于SW26010处理器,对该编译框架进行了实现,测试结果表明,该编译框架能够实现一些程序以面向异构众核结构的并行变换,且获得较好的加速效果.

基于机器学习的迭代编译方法是当前迭代编译领域的研究热点,其挑战在于学习算法选择、优化参数搜索及程序特征表示等问题.基于集成学习技术提出一种优化参数组合自动预测方法 ELOPS.使用约束多目标粒子群优化算法对优化空间进行搜索,找到样本函数最佳优化参数组合;通过特征—类相关性度量方法对函数特征进行抽取;最后通过由函数特征和最佳参数组合形成的样本构建集成学习模型, 对新程序优化参数进行预测.基于两种平台,在NPB 测试集和大型科学计算程序上与现有方法进行对比.实验结果表明,ELOPS 方法比现有 方法具有更好的预测性能.

针对新的应用程序和目标平台通常需要使用编译器进行程序优化顺序选择,以提升目标代码性能迭代编译可使优化顺序选择过程自动进行,在允许的时间空间范围内尽可能多地执行程序的不同版本,但该方法是一种机械式搜索,缺少对先前获得经验的利用,需要较大的执行开销.因此,需要能自动预测变换后目标程序性能而不必实际运行程序的优化编译方法提出一种编译器优化顺序选择方法:Features ANN该方法首先采用动静结合的程序特征表示技术,对程序特征进行抽取;然后基于程序特征对编译优化空间进行搜索,找到当前程序版本的最佳优化;最后,由程序特征和最佳优化形成训练样本,基于人工神经网络(artificial neural network,ANN)形成监督学习模型,对新程序的最佳编译优化顺序进行预测.实验结果表明,Features ANN与2种现有迭代编译方法GraphDSE和ClusterDSE比较时,在2种平台上相对于编译器标准优化级别-03分别获得1.49x,1.25x,1.38x和1.41x,1.16x,1.22x的执行时间加速比此外,与现有非迭代编译方法相比时,Features ANN也获得了有效的性能提升.

SIMD指令在大多数现代处理器架构中是必需的拓展部件.使用SIMD指令能同时对一组数据执行相同操作,从而实现空间上的并行性,显著提高处理性能.因此SIMD指令在二进制文件中指令的比例显著提高.但大部分动态二进制翻译器忽视了SIMD指令的翻译,源平台的SIMD指令常被翻译为一系列的标量指令,即要求目标平台拥有对应的SIMD指令支持此类并行计算.文章以申威国产处理器为实现平台,提出基于QEMU系统翻译SIMD指令优化方法,包括两个方面,一是借助修改已在QEMU中实现的helper函数,二是使用新引进的向量中间表示提高翻译系统QEMU对SIMD指令的翻译效率.前端为IA32平台,优化后的QEMU翻译对源平台的文件取得较好的加速效果.

基于机器学习的迭代编译方法可以在对新程序进行迭代编译时,有效预测新程序的最佳优化参数组合。现有方法在模型训练过程中存在优化参数组合搜索效率较低、程序特征表示不恰当、预测精度不高的问题。因此,基于机器学习的迭代编译方法是当前迭代编译领域内的一个研究热点,其研究挑战在于学习算法选择、优化参数搜索以及程序特征表示等问题。基于监督学习技术,提出了一种程序优化参数预测方法。该方法首先通过约束多目标粒子群算法对优化参数空间进行搜索,找到样本函数的最佳优化参数;然后,通过动静结合的程序特征表示技术,对函数特征进行抽取;最后,通过由函数特征和优化参数形成的样本构建监督学习模型,对新程序的优化参数进行预测。分别采用k近邻法和softmax回归建立统计模型,实验结果表明,新方法在NPB测试集和大型科学计算程序上实现了较好的预测性能。

对现有的编译器而言,间接数组索引不能被高效地向量化,这使得程序中包含有该类访存形式的间接数组索引不能利用SIMD扩展部件,这也是程序向量化研究中的热点问题。为了高效地利用SIMD扩展部件,充分挖掘程序中的向量化潜能,提出了一种对间接数组索引进行向量化的新方法,且提供了性能收益方法,分别对各种间接数组索引进行性能收益分析。实验结果表明,使用该向量化方法可以显著地提高程序的执行效率。

Iterative compilation based on machine learning can automatically predict the best optimization for the new programs. However, the efficient prediction models often require repetitive training, which leads to a higher training time overheads, and greatly affects the widespread utilization of the technology. The existing approaches in the prediction model construction often use random sample search strategy, which easily lead to data redundancy. In addition, due to the effect of run-time noises, the sample program is subjected to a fixed number of repetitive observations. However, in the case there is very little noises, the repetitive observations will result in a serious waste of iterative compilation time overheads. Therefore, how to effectively collect the optimal prediction model samples and choose the appropriate sample observations number are the key problem of reducing the iterative compilation overheads. We propose a low overheads iterative compilation optimization parameters prediction model ALIC. First, we describe the target programs by static-dynamic features representation based on feature-class relevance, and construct an initial optimization prediction model by the classifier. Then we use a dynamic number of sample observations strategy for each sample. The most profitable sample from the candidate samples set is selected and marked, each mark is equivalent to increase the number of sample observations. Finally, the optimization prediction model is constructed based on the intermediate prediction model that learns candidate samples actively. The experimental results show that when predicting optimization parameters for the new programs on Intel Xeon E5520 and Chinese Shenwei 26010 platforms, the ALIC model generates 1.38× (by ICC14.0 compiler), 1.35× (by GCC5.4 compiler) average performance improvement on the Xeon platform, and 1.42× (by SW compiler) on the Shenwei Platform. In addition, the ALIC model can significantly reduce the iterative compilation training time overheads than the existing approaches.

基于多面体模型的编译技术发展近30年,已经在多个开源编译器和商业编译器中得到了应用和实现.与传统的编译优化模型相比,多面体模型具备应用范围广、表示能力强、优化空间大等优点,代表了程序自动并行化领域众多方向最先进的水平,成为国际上多个编译研发团队的研究热点;同时,多面体模型抽象程度高、实现难度大、面临问题多的特征,阻碍了基于该模型的编译技术在发展相对滞后地区的普及,形成国内专门从事该问题研究的团队屈指可数的现象.为了打开多面体模型的"黑盒子",首先描述了多面体模型的原理,揭示了基于多面体模型的编译流程,并指出了该领域的主要研究内容;接下来,从程序并行性、数据局部性和其他领域上的扩展应用这3个方面对该领域上的研究进展进行了介绍;最后,对该研究领域当前面临的挑战和潜在的研究方向进行了总结.研究目的是通过回顾和总结基于多面体模型的编译技术研究进展,为国内编译研发团队提供重要参考,以期推动我国在该领域上的发展.

The SIMD (Single Instruction Multiple Data) extension component has been widely used in modern processors to improve the execution efficiency of the program. The mainstream compilers (such as GCC, ICC, OPEN64, etc.) have supported the SIMD automatic vectorization. Most current compilers can only vectorize the innermost layer of the loop, but this way often does not get the optimal performance promotion. Aiming at this kind of problem and combining with the processor architecture, a loop-nest vectorization method based on the benefit analysis model is proposed and implemented in the GCC compiler. This method can analyze different loop-nest vectorization schemes effectively and choose the most profitable one as the final optimization scheme. This article first reviewed the researches about loop-nest vectorization, then introduces this new code generation method for loop-nest vectorization. Finally, we use several common application examples for experiment. The experimental results show that the results of the benefit model are similar to the actual test results, and accordingly increase the efficiency for loop-nest vectorization.

Most CPUs in heterogeneous systems are now equipped with SIMD (Single Instruction Multiple Data) extensions that operate on short vectors in parallel to enable high performance. Refactoring programs for such systems relies on vectorization, i.e., transforming into a form with SIMD-instructions. We improve the state of the art in refactoring loops with nested IF-statements that are notoriously difficult to vectorize. For IF-statements whose conditions are independent of the loop variable, we improve the classical loop unswitching method, such that it can tackle nested IFs. For IF-statements whose conditions change with loop iterations, we develop a novel IF-select transformation method: (1) it can work with arbitrarily nested IFs, and (2) while previous methods rely on either masked instructions or hardware support for predicated execution, our method works for SIMD extensions without such operations (as found, e.g., in IBM Power8 and ARM Cortex-A8). Our experimental evaluation for the SPEC CPU2006 benchmark suite is conducted on an SW26010 processor used in the Sunway TaihuLight supercomputer (#2 in the TOP500 list); it demonstrates the performance advantages of our implemented approach over the vectorizer of the Open64 compiler.