We study energy dissipation and propagation of information encoded by Josephson vortices in two types of circular shift registers: a) uniform registers composed of sections of discrete Josephson transmission lines (JTL) forming a closed loop with a flux pump allowing us to change the number of moving fluxons; b) nonuniform registers composed of sections of the regular JTL and sections of JTLs utilizing nSQUIDs - dc-SQUIDs with negative inductance between their arms - instead of single Josephson junctions (JJs). nSQUIDs are parametric devices with a flexible double-well potential that were proposed as components for reversible computing. For the uniform register, we demonstrate the energy dissipation per bit-shift operation below the Landauer's thermodynamic limit E-T=k(B)Tln2 up to propagation delays of similar to 0.7 ns, corresponding to the circular information motion with frequencies up to similar to 1.4 GHz. This does not contradict Landauer's minimum energy requirement for computations since information is not destroyed. For the nonuniform register, we find the minimum energy dissipation per bit shift of about 16ET and attribute this to a nonuniform movement of vortices and energy barriers between the regular JTL and nSQUID sections. Differences of Josephson vortex propagation in both types of circular registers are discussed based on the measured current-voltage characteristics, extracted effective resistance and the terminal speed of Josephson vortices, and their dependences on the number of moving vortices. nSQUID inductance connecting JJs to the ground leads to an unusual type of lossless discrete transmission line with frequency-dependent impedance and propagation speed, both different from the regular JTLs.

A variety of superconductor integrated circuits comprising six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm x 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers enabling their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, and distance between moats in two active ground planes (GPs), and containing up to three additional 'dummy' GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to 1.2 μT. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-μm-wide slit moats occupying <2 cooldowns, supporting the viability of VLSI superconductor digital circuits. We have found a strong enhancement of flux trapping outside of the moats in circuits with closely spaced GPs and determined a critical distance, t_c=0.6 μm, between them. The presence of GPs spaced below t_c rendered the circuits nonoperational in 100 >3M JJs and determined individual cell margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier cells in the statistical distribution of the individual cell margins, we detected about one defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.

A variety of superconductor integrated circuits composed of six ac-powered SFQ shift registers with a total of 27078 bits and 108500 Josephson junctions (JJs) per 5 mm x 5 mm chip have been designed, fabricated, and tested to characterize flux trapping, fabrication process yield, and parameter spread. The six 4513-bit registers in the circuits have a common single-phase ac clock and individual input/output drivers, allowing for their parallel testing. We have investigated flux trapping in the circuits with various geometry, size, distance between moats in active ground planes (GPs), and containing up to three additional 'dummy' GPs, using multiple cooldowns through the critical temperature with various cooling rates and residual magnetic fields up to similar to 1.2 mu T. For the slit-type and square moats arrayed along the sides of the register cells, we have found a negligible effect of flux sequestered in the moats on the operating margins of the registers, and a negligible probability of detrimental flux trapping outside of the moats. Circuits with 0.3-mu m-wide slit moats occupying less than 2% of the circuit area were fully operational in 100% of cooldowns, supporting the viability of a very large-scale integration of superconductor digital circuits. We have also found a strong enhancement of flux trapping outside the moats in circuits with closely spaced GPs and determined a critical distance, t(c) approximate to 0.6 mu m, between them. The presence of two or more GPs spaced below the t(c) rendered the circuits nonoperational in 100% of cooldowns. We have measured 30 chips with over 3M JJs and determined individual cell operating margins in 138 registers to characterize the fabrication-related parameter spread and detect fabrication defects and flux-trapping events. By finding outlier bit-cells in the statistical distribution of the individual cell margins, we detected about one fabrication defect per million JJs, in most cases causing magnetic flux trapping in the affected cell.The circuits have been fabricated in the SFQ5ee fabrication process at MIT Lincoln Laboratory (MIT LL).

Superconductor electronics (SCE) appear promising for low energy applications. However, the achieved and projected circuit densities are insufficient for direct competition with CMOS technology. Original algorithms and nontraditional architectures are required for realizing SCE energy advantages for computing. Neuromorphic computing (NMC) is a commonly discussed deviation from conventional CMOS digital solutions. Instead of mimicking a conventional network of artificial neurons, we compose a network from the previously demonstrated single flux quantum (SFQ) electronics components which we termed bioSFQ. We present a design and operation of a new neuromorphic circuit containing a 3x3 array of bioSFQ cells - superconductor artificial neurons - capable of performing various analog functions and based on Josephson junction comparators with complementary outputs. The resultant asynchronous network closely resembles a three-layer perceptron. We also present superconductor analog memory and the memory Read/Write interface implemented with the neural network. The circuits were fabricated in the SFQ5ee process at MIT Lincoln Laboratory.

Superconductor single flux quantum (SFQ) technology is attractive for neuromorphic computing due to low energy dissipation and high, potentially up to 100 GHz, clock rates. We have recently suggested a new family of bioSFQ circuits (V.K. Semenov et al., IEEE TAS , vol. 32, no. 4, 1400105, 2022) where information is stored as a value of current in a superconducting loop and transferred as a rate of SFQ pulses propagating between the loops. This approach, in the simplest case dealing with positive numbers, requires single-line transfer channels. In the more general case of bipolar numbers, it requires dual-rail transfer channels. To address this need, we have developed a new comparator with a dual-rail output. This comparator is an essential part of a bipolar multiplier performing an ${\bm{X}} \cdot {\bm{Y}}$ operation on two analog currents ${\bm{X}}$ and ${\bm{Y}}$ . The multiplier has been designed, fabricated, and tested. We also present bioSFQ circuits for implementing an analog bipolar divide operation ${\bm{Y}}/{\bm{X}}$ and a square root operation $\surd {\bm{X}}$ . We discuss strategic advantages of the suggested bioSFQ approach, e.g., an inherently asynchronous character of bioSFQ cells which do not require explicit clock signals. As a result, bioSFQ circuits are free of racing errors and tolerant to occasional collision of propagating SFQ pulses. This tolerance is due to stochastic nature of data signals generated by comparators operating within their gray zone. The circuits were fabricated in the eight-niobium-layer fabrication process SFQ5ee developed for superconductor electronics at MIT Lincoln Laboratory.

Superconductor electronics (SCE) is competing to become a platform for efficient implementations of neuromorphic computing and deep learning algorithms (DLAs) with projects mostly concentrating on searching for gates that would better mimic behavior of real neurons. In contrast, we believe that most of the required components have already been demonstrated during the long history of SCE, whereas the missing part is how to organize these components to efficiently implement DLAs. We propose a family of logic/memory cells in which stored multi-bit data are encoded by quasi-analog currents or magnetic flux in superconductor loops while transmitted data are encoded as the rate of SFQ pulses. We designed, fabricated, and tested some of the basic cells to demonstrate a proof of concept, e.g., a unipolar and bipolar multipliers based on Josephson junction comparators. We coined the term bioSFQ to clearly connote close but distinguishable relations between the conventional SFQ electronics and its new neuromorphic paradigm.

Superconductor electronics fabrication technology developed at MIT Lincoln Laboratory enables the development of VLSI digital circuits with millions of Josephson junctions per square centimeter. However, conventional DC and multi-phase AC biasing techniques already encounter serious challenges for scaling circuits above several hundred thousand junctions. In this work, we propose a novel AC-based biasing scheme for RSFQ-type logic families requiring DC bias. The major step toward this scheme is a superconducting AC/DC rectifier which we introduced at ASC 2014. We proposed to connect the rectifiers to "payload cells" via superconducting inductors with large inductance in order to reduce parasitic effects of flux quantization. Recently, we discovered that this powering scheme works even better at a much lower value of the inductance, when it is just sufficient to hold only one or two flux quanta in the inductive loop between the converter and the payload. In this case, flux quantization in the loop becomes beneficial because the value of current fed into the payload is defined by the value of the coupling inductance. Therefore, our AC/SFQ converter powers the payload cell by single flux quanta rather than by DC current. Such mode of operation is extremely energy efficient because energy is used only to recover the flux quantum consumed by the cell during the logic operation. We present designs of AC/SFQ converters comprising an AC/DC rectifier and a current conditioning circuit which we termed an SFQ filter. We also present test results and demonstrate AC/SFQ powering a payload circuit using circuits fabricated in a new, 150-nm node of Lincoln Laboratory fabrication technology using self-shunted Nb/AlO x -Al/Nb Josephson junctions with 600 μA/μm 2 critical current density and 200 nm minimum linewidth of inductors.

We review the existing fabrication processes for superconductor digital electronics and describe approaches to increasing the scale of integration of superconducting digital circuits from the current level of about one million Josephson junctions (JJs) on a 1-cm2 chip toward ten million JJs per chip. We present designs of ac-clocked Single Flux Quantum (SFQ) shift registers, convenient benchmarking circuits, in a 250-nm-linewidth superconductor electronics fabrication process developed recently at MIT Lincoln Laboratory (MIT LL). For shift registers using resistively shunted JJs with Josephson critical current density, J c of 100 μA/μm2, we achieved a record-high circuit density of 4.2·106 JJs per cm2, a factor of three higher than the previous record obtained in the MIT LL 350-nm-linewidth SFQ5ee process. Using self-shunted JJs with J c of 600 μA/μm2, we increased this record circuit density to 7.4·106 JJs per cm2.

A high statistics data sample of the decays of $$K^+$$ mesons to three charged particles was accumulated by the OKA experiment in 2012 and 2013. This allowed to select a clean sample of about 450 events with $$K^{+}\rightarrow \pi ^{+}\pi ^{-}\pi ^{+}\gamma $$ decays with the energy of the photon in the kaon rest frame greater than 30 MeV. The measured branching fraction of the $$K^{+}\rightarrow \pi ^{+}\pi ^{-}\pi ^{+}\gamma $$ , with $$E_{\gamma }^{*} > 30\ \hbox {MeV}$$ is equal to $$(0.71 \pm 0.05) \times 10^{-5}$$ . The measured differential branching fraction over photon energy is compared with the prediction of the chiral perturbation theory to $${\mathcal {O}}(p^{4})$$ . A search for an up-down asymmetry of the photon with respect to the hadronic system decay plane is also performed.

Long ago, current recycling or serial biasing technique was recognized as a promising solution for the reduction of bias current in VLSI dc biased digital superconductor circuits. Despite a significant number of declarations, not so many successful experiments have been reported so far. In the paper we discuss our recent experiments with serially biased 16-bit counter-flow RSFQ shift registers, connected by special interfaces that are able to transfer SFQ pulses between the galvanically isolated driver and receiver. The required functionality is achieved using a superconductor transformer with isolated input and output coils. The known drawback of such interfaces is their parasitic sensitivity to magnetic fields induced by remote currents. To depress this sensitivity we have implemented a special superconductor guard that uses six superconductor layers. We have achieved stable operations of such registers with 16 current recycling stacks. The circuits have been fabricated at MIT Lincoln Laboratory.

Arrays of vortex transitional (VT) memory cells with functional density up to 1 Mbit/cm 2 have been designed, fabricated, and successfully demonstrated. This progress is due to recent advances in design optimization and in superconductor electronics fabrication achieved at MIT Lincoln Laboratory. As a starting point, we developed a demo array of VT cells for the 100-μA/μm 2 MIT LL fabrication process SFQ5ee with eight niobium layers. The studied two-junction memory cell with a two-junction nondestructive readout occupied 168 μm 2 , resulting in an over 0.5 Mbit/cm 2 functional density. Then, we reduced the cell area down to 99 μm 2 (corresponding to over 0.9 Mbit/cm 2 functional density) by utilizing self-shunted Josephson junctions (JJs) with critical current density JC of 600 μA/μm 2 and eliminating shunt resistors. The fabricated high-JC memory cells were fully operational and possessed wide read/write current margins, quite close to the theoretically predicted values. We discuss approaches to further increasing the integration scale of superconductor memory and logic circuits: 1) miniaturization of superconducting transformers by using soft magnetic materials; and 2) reduction of JJ area by using planar high-JC junctions similar to variable thickness bridges.

A precise measurement of the vector and axial-vector form factors difference $$F_V-F_A$$ in the $$K^+\rightarrow {\mu ^+}{\nu _{\mu }}{\gamma }$$ decay is presented. About 95K events of $$K^+\rightarrow {\mu ^+}{\nu _{\mu }}{\gamma }$$ are selected in the OKA experiment. The result is $$F_V-F_A=0.134\pm 0.021(stat)\pm 0.027(syst)$$ . Both errors are smaller than in the previous $$F_V-F_A$$ measurements.

Testing of Sequential circuits can be done by two test vectors (all 1&apos;s and all 0&apos;s) if the circuits were based on the conservative logic. The circuit is made to be tested by designing the circuit with the help of Reversible logic gates. Toffoli gate is used as reversible gate in this paper. Sequential circuits such as latches, flip flops are designed with the help of conservative logic reversible gate. Therefore, testing does not require any scan path access to the internal

A high statistics data sample of the \(K^{+}\rightarrow \mu ^{+}\nu _{\mu }\) decay was accumulated by the OKA experiment in 2012. The missing mass analysis was performed to search for the decay channel \(K^{+}\rightarrow \mu ^{+}\nu _{H}\) with a hypothetic stable heavy neutrino in the final state. The obtained missing mass spectrum does not show peaks that could be attributed to existence of stable heavy neutrinos in the mass range \((270< m_{\nu _{H}} < 375)\) MeV\(/c^{2}\). As a result, upper limits on the branching ratio and on the value of the mixing element \(|U_{\mu H}|^{2}\) are obtained.

Recent results from OKA setup concerning form factor studies in K e 3 decay are presented. About 5.25 M events obtained for decays of 17.7 GeV/ c K + are selected for the analysis. The linear and quadratic slopes for the decay form factor f + ( t ) are measured: λ' + = 2.95 ± 0.022 ± 0.018 × 10 -2 for the linear slope fit and λ + = 2.611 ± 0.035 ± 0.028 × 10 -2 , λ" + = 1.91 ± 0.19 ± 0.14 × 10 -3 for the quadratic one. The scalar and tensor contributions are compatible with zero. Several alternative parametrizations are tried: the Pole fit parameter is found to be M V = 891 ± 3 MeV; the parameter of the dispersive parametrization is measured to be Λ + = 2.458 ± 0.018 × 10 -2 .

Magnetic flux trapping is a serious problem in both low-temperature (LTS) and hightemperature (HTS) thin-film superconductive quantum interference devices (SQUIDs) and Josephson junction circuits. Trapped vortices in Josephson junctions can significantly degrade SQUID properties or even make them completely non-functional. Vortices can be trapped in superconducting films during the cooling process or can be caused by transient currents during current switching, electrostatic discharges through cable connections, etc. Unavoidable flux trapping happens in SQUIDs when a strong external field is applied. It can be a magnetization field in the case of superparamagnetic relaxation measurements (SPMR) or a pre-polarization field in the case of ultra-low field magnetic resonance imaging (ULF MRI), when an unshielded thin-film SQUID-based gradiometer is used. SQUID sensors stop working after being exposed to magnetic fields of only a few Gauss in strength. The most common way to remove frozen vortices is heating up a SQUID chip above its critical temperature which removes trapped fluxes and returns a SQUID to a normal operation. However, heating up a whole chip is usually too slow, is not reliably repeatable and dissipates too much energy. Earlier, we proposed a new alternative method for fast removal of trapped vortices in superconducting thin films by applying sinusoidal decaying magnetic field in an orthogonal direction. We called this method an alternating current or AC de-fluxing technique. In this paper we compile results obtained using planar thin-film LTS SQUID gradiometers and thin-film HTS SQUID magnetometers with bicrystal Josephson junctions. This new inductive AC de-fluxing technique is much faster than a conventional thermal cycling and dissipates significantly less energy. The technique was successfully tested with multiple LTS and HTS SQUID sensors. Finally, we discuss a possible mechanism to explain the observed inductive de-fluxing effects. We propose vortex-antivortex annihilation as a plausible mechanism explaining the observed inductive de-fluxing effects.