软件流水是一种重要的指令调度技术,它通过同时执行来自不同循环迭代的指令来加快循环的执行时间.随着处理器速度和访存速度差距越拉越大,访存指令尤其是cache miss的访存指令日益成为系统性能提高的瓶颈.由于这些指令的延迟不是固定的,如何在软件流水中预测并掩盖这些访存指令的延迟是非常重要的.与前人预测访存延迟的方法不同,引入cache profiling技术,通过动态收集到profile信息来预测访存延迟,并进行适当的调度.当增加模调度循环中的访存指令的延迟时,启动间隔也会随之增大,导致性能不会随之上升.CSMS算法和FLMS算法在尽量不增大启动间隔的情况下,改变访存指令的延迟.改进了CSMS算法和FLMS算法,根据cache profiling的信息来改变访存延迟,所以比前人的方法更为准确.实验表明,新方法可以有效地提高程序性能,对SPEC2000测试程序平均性能提高1%左右,个别例子的性能改进高达11%.

With the gap between the speed of processor and memory become wider and wider, memory access instruc- tions especially frequently cause cache miss are the bottleneck of the performance. As the compiler does not know the exact cycles of memory access instructions, it assumes the memory access instructions always hit or miss. So this is not accurate. We introduces cache profiling, which collects run time cache miss or hit information of memory access in- structions. Then we use this information to calculate the latency of these instructions. On out-of-order machine the hardware instruction scheduler can schedule the instruction inside issue window well, and the compiler have advantage on scheduling the instruction of long distance. Once cache miss occurs, reorder buffer may easily be full, causing the stall of pipeline. Then scheduling the instruction frequently causes cache misses, trying to paralleling them, can hide the long latency of cache misses and improve the performance. So we adjust the latency of the instruction frequently cause cache misses, and modify the scheduling policy, trying to improve memory level parallelism. Experiment shows that our scheduling policy can improve the performance 1.5%on average, with bzip2 4.8%and art 4%.

内联是编译器中的一种重要的优化手段.传统的编译器中内联模型只考虑函数的执行频率和大小,而没有考虑后面的优化.优化指导的内联模型是以考虑后面的优化为主而进行的内联,但它的缺点是没有考虑函数的执行频率和大小.为了克服以上两者的缺点,提出新的内联模型——循环合并敏感的优化内联模型,既考虑执行频率和函数大小,又考虑后面的优化.实现了考虑循环合并的内联,加入到ORC原有的内联模型中,自适应的建立新的内联模型,并对此模型进行性能调优.通过实验,发现热度这一内联标准在某些情况下不是很有效,并分析了原因,减少一些内联的函数,则会提高性能.实验的结果显示,新的内联模型可以有效地提高编译器的性能,某些SPECCPU2000实例的peak性能有高达6%的性能提升,平均提升1%.

How to reduce and hide the latency of cache misses is the focus. To get the information of cache references, we often need to run simulators, which is very slow. To overcome this, this paper introduces cache profiling in compile without need of simulator. Similar to value profiling and stride profiling, cache profiling instruments instruct referencing memories, which can improve the speed significantly and only need the support of compiler. The information got from cache profiling can be used for the improvement of instruction scheduling, software prefetching, generating cache hints and helper threads.