With the development of high speed communication system and the improvement of the transmission speed, Phase Lock Loop(PLL) to be the core circuit of providing precision clock has been put forward higher request, not only required to produce low jitter and low noise clock, but also demanded wide frequency range and multi-protocol supportment. As the core module of PLL, the performance of the phase noise and frequency range of voltage control oscillation(VCO) directly influence the quality of transmission clock. To reach the different transmission frequency requirement of multi-protocol, a 6.5-to-11 GHz LCVCO with wide-frequency-range and low-phase-noise is designed. Using 6-bits frequency –band-selected signal to control tuning capacitor array for relalizing the division and adjustment of the output frequency, and design optimal Kvco within each band to cover all frequency points with low phase noise. This chip is fabricated in 40 nm CMOS process, the simulation results shown that the output frequency is from 6.5 GHz to 11 GHz and the phase noise is below 107.1 dBc@1 MHz.

In order to enhance the performances of clock and data recovery circuit(CDR) in the high speed multichannel serial transceiver system, a novel phase interpolator(PI) circuit used in CDR has been proposed in the paper. It adopts four groups of differential signal and DAC to act on common load resistance, generates complementary thermometer code through digital filter to control DAC output current, realizes phase weight allocation for differential input clock to make 128 times interpolated, and optimizes the differential signal by input stage four phase correction circuit and duty cycle adjustment circuit. This chip is fabricated in 40 nm CMOS process, the simulation results show that PI has good linearity from 1 GHz to 6 GHz, and DNL is no more than 1.4 LSB, INL is no more than 1.5 LSB, and has been successfully applied to a variety of high speed SerDes.

为了在高速传输系统中实现宽频带和低抖动时钟输出的要求,设计了一种基于Ring-VCO结构的低抖动锁相环,采用与锁相环锁定频率强相关的环路带宽调整方法来降低环路噪声,加速环路锁定,即利用全局参考调节电路中比较器模块将锁定控制电压与参考电压比较来改变各模块电流,根据不同锁定频率调整环路参数,大大缩短了锁定时间,同时利用四级差分环形振荡器和占空比调整电路的差分对称结构,降低了电路噪声.电路采用40 nm CMOS工艺实现,测试结果表明输出频率为1.062 5 GHz～5 GHz,在最高时钟频率5 GHz下眼图质量良好,时钟抖动39.6 ps.

在传感器系统中,为了能够得到精确的数据,需要对传感器信号进行补偿和处理.传感器信号调理芯片正是对传感器信号进行调理的一种技术.在现有信号调理芯片的基础上,提出了几种信号调理芯片应用解决方案,实现补偿校准、环路供电等功能.同时通过解决方案的几种典型应用案例,阐述了解决方案在系统中的使用.与传统的信号调理方法相比,这些解决方案减少了元器件使用,降低了功耗,可以用于运算放大器、仪表放大器等设备,从而满足不同档次产品的需求.