We investigate the threshold voltage $(\boldsymbol{V}_{\text{th }}$) distribution of a 176-layer TLC vertical NAND (VNAND) flash memory by experimentally decomposing it into physically distinct components. The measured distribution is separated into an ideal baseline defined by programming conditions, intrinsic broadening evaluated at the page-level, and interaction-induced contributions emerging at the block-level. Intrinsic variation is dominated by read variation including random telegraph noise (RTN), while initial $V_{\text{th }}$ shift (IVS) also contributes to distribution degradation. Among interaction effects, word-line (WL) coupling induces width broadening, whereas other mechanisms primarily cause $\boldsymbol{V}_{\text{th }}$ shift without distribution widening. This decomposition clarifies which degradation components are practically improvable and which are fundamentally constrained by device architecture and operation.

For the first time, 900 -layer class VNAND integration was implemented by bonding two 450 -layer cell wafers. The cell wafer with a large warpage could be successfully supported in the upper chuck through an appropriate warpage design during bonding process, and the alignment deterioration that occurs in bonding between cell wafers with large warpage was also solved by applying new overlay correction technology. In addition, normal cell operation characteristics were verified based on the newly introduced the bit-line (BL) and word-line (WL) structure that can drastically improve the power consumption and chip size.

The challenge of evolving to create a memory that is shrinking compared to the previous generation while satisfying the high performance and low power required for flash memory has been present in every generation, but the recent rapid change to artificial intelligence (AI) trends is very tough, as the level of demand is increasing sharply. The IO speed required for PCs, mobile devices, and servers is rapidly increasing, and low power for large-capacity applications is also very important as it is directly related to performance. At the peak of this change, our tenth-generation nand changed the structure to 3-D bonded vertical nand (BV-NAND) and successfully developed high-density memory with three stacks of 4XX wordline (WL) and zero dummy hole. The highest IO speed of 5.6 Gb/s and the extremely low power are also achievements.

NAND flash memory industry has made significant progress in the density and technology since the introduction of 3D NAND flash memory. It took only a few years to change the mainstream of the NAND flash memory from 2D NAND to 3D NAND thanks to its superior cell characteristics with bit cost scalability in spite of the difficulties in process. Up to now, 3D NAND technology also has been advancing rapidly, driving bit growth scaling with the increase in the number of vertical word lines. However, NAND flash memory industry is constantly encountering the new challenges in terms of the capacity and performance. In this paper, we review trends and key technologies during the evolution of 3D NAND flash memory and the challenges NAND industry need to solve to meet the growing market requirement.

An industry leading 128-layer single-stack 3D-NAND Flash memory with high reliability cell characteristics is successfully developed for the first time. Single-stack etching of 128 layers brings about various deformation of hole profile, which leads to the degradation of cell characteristics. The degradation of cell characteristics has been overcome by advanced HARC (high-aspect ratio contact) etching process and ONO material engineering. The single-stack NAND Flash memory still has a potential to be developed further with the advanced single-stack technology.

In this work, we present a true 3D 128 Gb 2 bit/cell vertical-NAND (V-NAND) Flash product for the first time. The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1x nm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution. Also, a negative counter-pulse scheme realizes a tightly programmed cell distribution. In order to reduce the effect of a large WL coupling, a glitch-canceling discharge scheme and a pre-offset control scheme is implemented. Furthermore, an external high-voltage supply scheme along with the proper protection scheme for a high-voltage failure is used to achieve low power consumption. The chip accomplishes 50 MB/s write throughput with 3 K endurance for typical embedded applications. Also, extended endurance of 35 K is achieved with 36 MB/s of write throughput for data center and enterprise SSD applications.