This article presents a cryogenic CMOS quantum state controller (QSC) application-specific integrated circuit (ASIC) for frequency-division-multiplexing (FDM) access of multiple qubits concurrently. A low-jitter accumulated tunable mixer-based frequency comb (TMFC) is proposed for multiple quadrature carrier generation with low power consumption while keeping jitter accumulation bounded. In each TMFC stage, the quadrature-input quadrature-output mixer is loaded with a Q-boosted tunable $LC$ -tank using a cross-coupled negative-transconductance cell, filtering out unwanted spurs. The vector modulator is applied to adjust the relative phase between carriers to set the effective rotation axis and interaction direction in multiqubit gates. A digital power amplifier (DPA) comprising 256 thermometer-coded unit cells is used for envelope modulation. For flux-bias control, the $Z$ -path driver uses a hybrid pulse-density modulation (PDM) scheme, extending the effective resolution of an area-efficient 8-bit current-steering digital-to-analog converter (DAC) core. Fabricated in a 65nm CMOS process and measured at 4K, the ASIC integrates four $XY$ driving paths and four $Z$ driving paths, achieving a competitive power efficiency of 11.4mW/qubit. Electrical characterizations demonstrate a spurious-free dynamic range (SFDR) of >42dBc for the $XY$ -path, while the $Z$ -path driver exhibits good static linearity and pulse-transition characteristics. Quantum control experiments conducted in a dilution refrigerator validate the functional operation of both the $XY$ and $Z$ paths, establishing the proposed QSC as a promising scalable solution for frequency-multiplexed superconducting-qubit control.
A jitter-filtering retimer is presented, cascading a wide-bandwidth injection-locked oscillator (ILO)-based clock and data recovery (CDR) unit with a narrow-bandwidth jitter-filtering phase-locked loop (PLL). Achieving both high input jitter tolerance (JTOL) and low output jitter typically presents a contradictory design requirement, as widening the tracking bandwidth to improve JTOL inherently allows more jitter to pass through to the output. The proposed architecture resolves this tradeoff by decoupling the tracking and filtering: the ILO-based input CDR provides rapid phase tracking for high-frequency jitter, while the subsequent $LC$ -PLL generates a jitter-filtered transmitter clock. The input CDR employs a quarter-rate architecture and utilizes a digital loop filter (DLF) with data transition pattern filtering to ensure robust control of the input delay line and ILO frequency. Fabricated in 28-nm CMOS technology, the proposed retimer operates from 12 to 20 Gb/s and consumes 58.66 mW at 20 Gb/s. Measurement results demonstrate the widest-reported 20-Gb/s JTOL of $1~\text {UI}_{\text {pp}}$ at a sinusoidal jitter (SJ) frequency of 173 MHz, with a measured JTOL bandwidth of approximately 500 MHz, verifying the capability to achieve superior JTOL while minimizing the impact on output jitter performance.
This article presents a split-tail CMOS Gilbert-cell frequency doubler and its use in a wideband mmWave frequency octupler. The proposed doubler operates with a reduced switching duty cycle, enabling high conversion gain (CG) and improved current efficiency while providing high suppression of undesired harmonic components. A standalone implementation of the doubler in 28-nm CMOS FD-SOI achieves Psat = 9.5 dBm and 7.3-dB CG. The total efficiency and power-added efficiency are 15% and 11%, respectively. Leveraging the high gain of the doubler, a three-stage octupler is realized in 55-nm CMOS without interstage amplifications. To mitigate harmonic folding, a closed-loop biasing technique is applied to the first stages to stabilize the duty cycle and reduce generation of unwanted even-order harmonics. The octupler achieves up to 7 dBm output power at 83 GHz with a 47% fractional bandwidth. The total harmonic rejection (THR) exceeds 40 dBc at 41% bandwidth, from 67 to 102 GHz. The total efficiency is 7% while, thanks to the high overall CG of 17 dB, the peak PAE is 6.5%.
This article presents a novel charge-pump (CP) analog-to-digital converter (ADC) architecture supporting a $2\times $ VDD input range under a single supply voltage, VDD, and improving the dynamic range (DR) for next-generation, low-voltage, low-power, and high-precision signal-chain applications. The local passive-reference boost (PRB) technique is proposed using a CP circuit to internally double the reference voltage to $2\times $ VDD, thereby doubling the input range and increasing the DR. Furthermore, CP floating inverter amplifiers (CP-FIAs), employed in the noise-shaping (NS) filter, also boost their analog voltages to $2\times $ VDD, addressing the low-voltage design challenge in analog circuits. In addition, an NS-assisted charge-balance-calibration (NS-CBC) technique is proposed in this work to calibrate bit-weight errors caused by on-chip passive reference droop and compensate for mismatch errors. Fabricated in a 65-nm CMOS process, the 0.6-V NS-SAR ADC supports a 1.2-V input range and achieves 93.5-dB SNDR. With a power consumption of 975.6 nW, it achieves the Schreier FoM (FoMs) of 183.6 dB. It also maintains a stable SNDR within 4 dB and FoMs across process/voltage/temperature (PVT) variations and sampling-frequency scaling.
Electrostatic-force actuation is widely used in Micro-electromechanical Systems (MEMS) capacitive sensors such as accelerometers with self-test, force balancing, or electrostatic damping. Unlike conventional capacitive-to-voltage converters (CVCs) optimized only for charge sensing, this article proposes a variable-input-bias-amplifier (VBA)-based CVC for concurrent sensing and electrostatic-force actuation, which breaks the noise-size tradeoff of the MEMS capacitive sensor. This article further presents the mathematical model, key parameters, and circuit implementations of the VBA architecture. The proposed VBA-based CVCs are fabricated in a commercial $\mathbf {0. 1 8}$ - $\boldsymbol {\mu } \mathbf {m}$ CMOS process and tested with a MEMS capacitive accelerometer. Measurement results show that the Type-IV VBA-CVC achieves a maximum bias swing of 3.95 V with a 5-V supply and a minimum circuit noise of $13.9 {\,}{\,}\mathrm {zf}/(\mathrm {Hz})^{1/2}$ with 91.5- $\mu \mathrm {A}$ current consumption. The MEMS accelerometer with the VBA-CVC achieves a ±5-g self-test range and a minimum system noise of $\mathbf {4}{\,}{\,}\boldsymbol {\mu } \mathbf {g}/(\mathbf {H z})^{1/2}$ over a 300-Hz bandwidth with 91.6- $\mu $ A current consumption.
