To reduce the charge-coupled device(CCD) readout noise and improve the detection ability un-der low illumination and dim targets,a new low-noise CCD signal processing technology-CCD dig-ital denoise-is gradually being employed in aerospace detection and other fields.In this study,the main readout noise of CCD detectors and its characteristics are analyzed.A CCD digital denoise sys-tem and an experimental platform are designed as well as established by using a PCIe data acquisi-tion card.According to the characteristics of readout noise,some digital filters are analyzed and de-signed based on distributed kernel coefficient,and the optimal kernel coefficients are obtained through iteration.Then,CCD signal and filter model are established,and the optimal filter is de-signed to apply to the digital denoise system.Finally,according to the image data obtained from the system,the performance of the digital denoise system and digital filtering algorithm is evaluated and compared.At 500 kHz and 1 MHz CCD readout rates,the denoising performance of the optimal filter designed in the experiment is 16％-32％ higher than that of the digital filter with kernel distribution coefficient,and 50％-60％ higher than that of the traditional correlated double sampling technology.

Background Due to metabolic changes in the second trimester and the increasing number of pregnant women with obesity and advanced maternal age, the incidence of gestational diabetes mellitus (GDM) remains high. This study aimed to evaluate the effects of GDM on fetal cardiac morphology and function, and to determine whether these changes increase with increasing estimated fetal weight (EFW). Methods Fifty-eight women with GDM (GDM group) and 58 women with a healthy pregnancy (control group) were included in this prospective observational cohort study. Each group included subgroups of 31 pregnant women with a gestational age between 24 +0 weeks and 27 +6 weeks as well as 27 pregnant women with a gestational age between 28 +0 weeks and 40 +0 weeks. For all fetuses, a cine of 2–3 s in the four-chamber view was obtained, and online speckle-tracking analysis was performed using the GE Automatic Fetal Heart Assessment Tool (fetal HQ; General Electric Healthcare Ultrasound, Zipf, Austria) to measure the global sphericity index (GSI), global longitudinal strain (GLS), fractional area change (FAC), 24-segment sphericity index (SI), and 24-segment end-diastolic diameter of the left ventricle (LV) and right ventricle (RV). Data were analyzed using the independent t-test and Wilcoxon rank-sum test, as applicable. Results The GDM group (mean HbA1c value was 5.3 ± 0.57 mmol/L) showed a lower GSI value than the control group (1.21 vs. 1.27, P = 0.000), which indicated a rounder shape of the heart. In addition, fetuses in the GDM group demonstrated significant impairment in cardiac function compared to those in the control group (LV-GLS: -18.26% vs. -22.70%, RV-GLS: -18.52% vs. -22.74%, LV-FAC: 35.30% vs. 42.36%, RV-FAC: 30.89% vs. 36.80%; P = 0.000 for all). Subgroup analyses according to gestational age (24 +0 –27 +6 weeks and 28 +0 –40 +0 weeks) showed that the statistical differences were retained between the GDM and control groups in each subgroup. Conclusions Fetuses of women with GDM present with signs of biventricular systolic dysfunction according to deformation analysis using fetal HQ. Additionally, the heart had a rounder shape in the GDM group than in the control group. This study showed that fetal HQ can be used to assess fetal cardiac morphology and function easily and quickly, and the effects of GDM on fetal cardiac morphology and function appeared from the second trimester. Thus, whether earlier and stricter clinical intervention was necessary remained to be further studied. Furthermore, future studies will need to supplement the effects of blood glucose levels on GLS, FAC, GSI, and 24-segment SI. Additionally, the long-term follow-up after birth should also be improved to observe the influence of changes in the indicators on the prognosis.

目的 探讨超声多参数对妊娠期糖尿病?(GDM)?患者中孕期胎儿心脏功能的评估价值.方法 选择2020年4月至2020年10月中国医科大学附属盛京医院诊断为GDM的中孕期孕妇62例作为GDM组,选择同期进行胎儿心脏超声检查的健康中孕期孕妇30例作为对照组.所有孕妇自愿参加本研究并签署了知情同意书.所有孕妇均进行空腹血糖、口服葡萄糖耐量测试,GDM组孕妇测量糖化血红蛋白值.采用GE公司的Voluson?E10超声诊断仪进行胎儿整体评估,并使用多参数评价胎儿心脏功能变化.结果 2组胎儿整体超声评估均未发现明显畸形,2组胎儿胎龄比较无统计学差异?(P?>?0.05?).与对照组比较,GDM组胎儿左、右心室的等容收缩时间?(IVCT)、等容舒张时间?(IVRT)、心肌性能指数?(MPI)?增大?(均P?0.05).而二尖瓣舒张早期血流速度,二尖瓣舒张晚期血流速度,二尖瓣舒张早、晚期流速比值,三尖瓣舒张早期血流速度,三尖瓣舒张晚期血流速度,三尖瓣舒张早、晚期流速比值,左心室射血时间2组比较无统计学差异?(均P?>?0.05).GDM组胎儿左心室IVCT、右心室IVCT、MPI均与胎龄正相关?(均P?0.05).?结论 与正常孕妇胎儿比较,GDM孕妇胎儿心室IVCT、IVRT、MPI增大,提示GDM胎儿心脏功能可能受损.组织多普勒超声下测量的IVCT、IVRT、MPI指标能够便捷快速评估胎儿心脏功能的改变.

Abstract Introduction: The current study aimed to assess the efficacy of a new scanning procedure in fetal cardiac screening by 6 planes in the upper mediastinum. Methods: This is a prospective study. 123 normal fetuses without extracardiac abnormalities or CHD were enrolled in this study totally. Two sonographers with similar experience were trained for one month about how to obtain the added planes. Sonographer A used Color Doppler combined with the radiant flow (Color-R-flow) while sonographer B used high definition flow imaging combined with the radiant flow (HD-R-flow) to display 6 planes in the upper mediastinum. The difference between these two color modalities in subgroups of different fetal positions (supine, prone, and lateral position) was also discussed. Results: HD-R-flow has higher detection rates of the 6 planes than Color-R-flow. The differences presenting for the left innominate vein and azygos vein (LIV and AzV) view, bilateral subclavian arteries (BSA) view, and the bilateral internal thoracic arteries (BITA) view were significant (P<0.01). The results also demonstrated that HD-R-flow showed significantly higher detection rates than the Color-R-flow for the LIV and AzV view and the BITA view of the fetuses in the supine and lateral position, and BSA view of fetuses in lateral position. Conclusion: The current study introduced an enhanced scanning procedure to assess vessels in the fetal upper mediastinum. A new color-imaging technique was used to better show tiny vessels. This has confirmed its value in showing a satisfactory detection rate for the 6 cardiac planes.

A 3GS/s 12-bit current-steering digital-to-analog converter (DAC) fabricated in 55 nm complementary metal–oxide–semiconductor (CMOS) technology has been presented. A partial randomization dynamic element matching (PRDEM) method based on switching sequence optimization is proposed to mitigate the mismatch effect and suppress the harmonic distortion with low hardware complexity. In the switching current cell, the cascode structure together with “always-ON” small current sources are used to keep the output impedance high and uniform. A compact layout of the switching current array is carefully designed, featuring short wires routing and small parasitic capacitance. According to the measured results at 3GS/s, this DAC demonstrates a spurious-free dynamic range (SFDR) of 74.64 dBc at low frequency and 50 dBc at 1.5 GHz output. The chip occupies an active area of 0.2 × 0.48 mm2 and consumes a total power of 495 mW.

This brief presents an 8 GSps 14 bit current steering RF digital-to-analog converter (DAC) for communication system. Double edge sampling method is adopted to reduce maximum clock frequency. To suppress the third-order intermodulation (IM3), current switch driver with enhanced reset circuit is proposed. An improved dynamic element matching (DEM) method based on optimized switching sequence is adopted. According to experimental result, the measured IM3 is below -62 dBc up to 3.6 GHz. The digital interpolation and up-converters block are included. Eight lane 10 Gb/s JESD 204B receiver are integrated. The chip is fabricated in 40-nm CMOS, with a die size of 2.75 x 3 mm(2).

In this paper, a time-interleaved 10-GS/s 8-bit analog-to-digital converter (ADC) fabricated in 0.18 mu m SiGe BiCMOS technology has been demonstrated. A 4 x 4 input multiplexer with good isolation and wide input bandwidth is proposed, which enables the ADC to support 1/2/4-channel sampling modes. In the track-and-hold (THA) stage, a switched emitter follower (SEF) topology with delayed dummy clock is introduced to minimize the overshoot effect of the SEF output. The ADC achieves spurious free dynamic range (SFDR) > 52 dBc and effective number of bits (ENOB) > 6.8 in low input frequencies. The analog input bandwidth is 5.6 GHz.

This paper presents a broadband DC-coupling master-slave sample-and-hold amplifier (SHA) in 0.13 mu m SiGe BiCMOS process. PMOS source follower is implemented as the input stage to realize DC coupling such that spectrum near DC can be utilized for spectrally efficient modulation schemes. The trade-offs among bandwidth, harmonic distortion and feedthrough are investigated in track-and-hold switches, to optimize its bandwidth specification and dynamic performance as well. The design is verified with an input signal of 0.6 Vpp, which is sampled at 16 GS/s: the results show a bandwidth of over 20 GHz; The total harmonic distortion (THD) is -40 dB for a 2.11 GHz input signal. The proposed SHA is suitable for high-speed broadband analog-to-digital converter used in microwave and optical communication. (C) 2019 Elsevier GmbH. All rights reserved.

A 5 GS/s 8-bit analog-to-digital converter (ADC) implemented in 0.18 μm SiGe BiCMOS technology has been demonstrated. The proposed ADC is based on two-channel time-interleaved architecture, and each sub-ADC employs a two-stage cascaded folding and interpolating topology of radix-4. An open loop track-and-hold amplifier with enhanced linearity is designed to meet the dynamic performance requirement. The on-chip self-calibration technique is introduced to compensate the interleaving mismatches between two sub-ADCs. Measurement results show that the spurious free dynamic range (SFDR) stays above 44.8 dB with a peak of 53.52 dB, and the effective number of bits (ENOB) is greater than 5.8 bit with a maximum of 6.97 bit up to 2.5 GS/s. The ADC exhibits a differential nonlinearity (DNL) of -0.31/+0.23 LSB (least significant bit) and an integral nonlinearity (INL) of -0.68/+0.68 LSB, respectively. The chip occupies an area of 3.9 × 3.6 mm2, consumes a total power of 2.8 W, and achieves a figure of merit (FoM) of 10 pJ/conversion step.

In this paper, a 1-GS/s 12-bit pipelined folding analog-to-digital converter (ADC) fabricated in 40 nm CMOS technology is presented. A new encoding algorithm based on distributed quantization is proposed to simplify the quantization process of the structure with odd folding factor and reduce the hardware consumption of the circuit. The ADC achieves spurious free dynamic range (SFDR) > 72 dB and signal-to-noise and distortion ratio (SNDR) > 57 dB in low input frequencies.

This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed master clock to suppress the time skew between channels. Based on the segmented pre-quantization and bypass switching scheme, double alternate comparators clocked asynchronously with background offset calibration are utilized in sub-channel SAR ADC to achieve high speed and low power. Measurement results show that the signal-to-noise-and-distortion ratio (SNDR) of the ADC is above 38.2 dB up to 500 MHz input frequency and above 31.8 dB across the entire first Nyquist zone. The differential non-linearity (DNL) and integral non-linearity (INL) are +0.93/−0.85 LSB and +0.71/−0.91 LSB, respectively. The ADC consumes 60 mW from a 1.2 V supply, occupies an area of 400 μm × 550 μm, and exhibits a figure-of-merit (FoM) of 348 fJ/conversion-step.